Recently, I have been carrying out some beginner to lower moderate level designs, from starting to all the way to HDL coding in verilog. I thought that FSM based design, either Mealy or Moore is the only option. However, while actually translating the design in verilog HDL, I had lots of trouble. Many times, the design would just not work the way it should because of timing related problems. Plus it took good amount of typing efforts as well.
Contrary to this approach, it took me quite less time and effort following a state-less approach for same designs, and , produced results. But maybe this could be because my designs are not too big at this stage.
So how do you decide whether to use a state based FSM model or stateless model in design ?
Is there some pattern while following any approach ? Or maybe some specific group of problems which should be solved only by state based approach ?
By state-less design, I mean creating / connecting already designed modules, alongwith some more new logic. Not quite structural modelling, combination of structural and behavioural modelling you can say.
I'm not asking about pros and cons of Mealy vs Moore.