3
\$\begingroup\$

Recently, I have been carrying out some beginner to lower moderate level designs, from starting to all the way to HDL coding in verilog. I thought that FSM based design, either Mealy or Moore is the only option. However, while actually translating the design in verilog HDL, I had lots of trouble. Many times, the design would just not work the way it should because of timing related problems. Plus it took good amount of typing efforts as well.

Contrary to this approach, it took me quite less time and effort following a state-less approach for same designs, and , produced results. But maybe this could be because my designs are not too big at this stage.

So how do you decide whether to use a state based FSM model or stateless model in design ?

Is there some pattern while following any approach ? Or maybe some specific group of problems which should be solved only by state based approach ?

By state-less design, I mean creating / connecting already designed modules, alongwith some more new logic. Not quite structural modelling, combination of structural and behavioural modelling you can say.

I'm not asking about pros and cons of Mealy vs Moore.

Thank you

\$\endgroup\$
6
  • 2
    \$\begingroup\$ I am not sure on your use of the term stateless. Verilog without state would be combinatorial logic, Output is pure combination of inputs without reference or bias from previous inputs, it has no memory or state. A design with out flip-flops or latches would be stateless. \$\endgroup\$ Jul 16 '15 at 8:19
  • \$\begingroup\$ @pre_randomize. By state-less, I mean not using state machine approach ie without using FSM. \$\endgroup\$ Jul 16 '15 at 8:20
  • \$\begingroup\$ I would have thought the problem your trying to solve dictated whether or not it required it. I do not understand the type of problem that could be solved with and without a state-machine approach you either require knowledge of the past or not. If your code does not look like a state machine but uses flip-flops then is it not just a non obvious state machine? maybe if you had an example of the problem it might help clarify. \$\endgroup\$ Jul 16 '15 at 8:25
  • 1
    \$\begingroup\$ If you build an FIR to filter data this includes lots of flip-flops but would not be called a FSM, but it is stateful holding previous values. FSM patterns tend to work well when dealing with sequences of inputs and deciding what state you want some thing to be in, or sending an output sequence, rather than conditioning data. \$\endgroup\$ Jul 16 '15 at 8:28
  • 1
    \$\begingroup\$ Does not sound a bad approach, especially if you take into account that it might spend a lot of time idle and you want to implement a low power state which stops the clock etc. 1 state machines Idle/Active do not often look like state machines though. The actual arithmetic part of the calculator should probably sit parallel to the controlling FSM though. \$\endgroup\$ Jul 16 '15 at 8:43
6
\$\begingroup\$

Even though a design may be considered 'stateless' because there is no explicit state machine, you may still be actually coding a type of state mechanism without explicitly calling it that. For example, flags may be used to indicate if one part of the code is busy or not. In your 'calculator' example, you may not have a state machine, but you may have a flag that indicates that data is available and ready for processing. Even though this may not be called a state machine, you are using flags or other signals as a mechanism to ensure that specific operations are performed in a certain sequence. You're essentially making a state machine using your flags.

As a result, a state machine is pretty much present in most things. An explicitly designed one is really just a way for the coder behind the keyboard to keep track of the process their system is going through to ensure that everything performs as expected. When a system is more complicated, this is a really useful mechanism because it's only possible to keep track of so much at once. If it's a simple design, it may just be necessary to use a couple of flags and be done with it. It really just comes down to how complicated the problem is.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.