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I am a beginner with FPGAs and EE in general, so please bear with me!

It is my understanding that many modern FPGAs are SRAM-based, and for good reason: SRAM can handle higher clock speeds and has lower standby current than DRAM. However, it is MUCH larger than DRAM.

So, say you had some kind of logic circuit that was absolutely enormous and you didn't care about speed at all. In this case, could it be plausible to use a DRAM-based FPGA (assuming you find a way to fix DRAM's parasitic reads)? Does such an FPGA even exist?

Additionally, how much smaller would a design on a DRAM-based FPGA be than on an SRAM-based FPGA?

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  • \$\begingroup\$ I don't think DRAM would be particularly useful for this as it requires controllers to continuously refresh the contents and would have a much more problematic access issues. Basically FPGAs are made of many small SRAM logic blocks with interconnect fabric and it is easy to make small SRAM blocks which is a completely different from how a DRAM is designed. \$\endgroup\$ – Tom Carpenter Jul 17 '15 at 1:48
  • \$\begingroup\$ Hey Tom, thanks for the response. What if you had placed the DRAM controllers "externally"? This is what I meant by fixing the parasitic reads. If you've ever heard of Micron's Automata Processor, it's basically an FPGA in DRAM! \$\endgroup\$ – Ted X Jul 17 '15 at 1:59
  • \$\begingroup\$ Interesting, not heard of the Micron thing before. Had a quick flick through the paper, but it seems that is a very specific task which couldn't be done efficiently in an FPGA (as opposed to being an FPGA in DRAM) - I could be wrong, only flicked through the paper. \$\endgroup\$ – Tom Carpenter Jul 17 '15 at 2:08
  • \$\begingroup\$ That's called a CPU. You can run an FPGA emulator on a CPU if you want. They're much more space-efficient when dealing with branching control flow. \$\endgroup\$ – user253751 Sep 22 '17 at 4:00
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http://isca2016.eecs.umich.edu/wp-content/uploads/2016/07/8A-1.pdf

There is a new research in ISCA, a prestigious conference on DRAM-based FPGA recentely.

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The configuration of an FPGA is stored in special SRAM cells (less transistors and lower static current) or in flash memory. This memory needs to be 'read' at every time otherwise the path transistors won't work. DRAM can't be read continously.

Producing normal CMOS logic and DRAM logic are different processes. DRAM needs other machines and materials. This is why embedded DRAM (eDRAM) is used in rare cases: mostly as large L4 cache or embedded main memory for uC.

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    \$\begingroup\$ It turns out that there's been limited research in DRAM FPGAs. In IEEE Transactions on VLSI 2013, Pan et al. used special MRAM cells to store configuration bits of a DRAM-based FPGA and were able to achieve significant area reduction of the FPGA die size. \$\endgroup\$ – Ted X Jul 17 '15 at 18:40
  • \$\begingroup\$ I would think that while dynamic "memory" as such wouldn't work, an FPGA that used dynamically-refreshed pass gates which were charged to a voltage above VDD might be more compact than one which relied upon statically-configured gates (if the logic that loads the gates can switch to a voltage above VDD and the addressing logic can switch a voltage below VSS, it would be possible to use NFETS, rather than NFET/PFET pairs, as pass gates, with the gate of each NFET controlled by a single PFET acting as a pass gate. Some other kind of memory would need to hold... \$\endgroup\$ – supercat Dec 8 '16 at 20:33
  • \$\begingroup\$ ...and continuously resupply the data to be loaded into all the pass gates, but that could be kept elsewhere on the chip. \$\endgroup\$ – supercat Dec 8 '16 at 20:34

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