I am a beginner with FPGAs and EE in general, so please bear with me!
It is my understanding that many modern FPGAs are SRAM-based, and for good reason: SRAM can handle higher clock speeds and has lower standby current than DRAM. However, it is MUCH larger than DRAM.
So, say you had some kind of logic circuit that was absolutely enormous and you didn't care about speed at all. In this case, could it be plausible to use a DRAM-based FPGA (assuming you find a way to fix DRAM's parasitic reads)? Does such an FPGA even exist?
Additionally, how much smaller would a design on a DRAM-based FPGA be than on an SRAM-based FPGA?