1
\$\begingroup\$

Some synchronous buck regulator ICs sport a NMOS lowside switch and a PMOS high side switch. I understand why these use a PMOS/NMOS pair instead of a NMOS/NMOS pair, but I can't seem to make sense of how one would drive the PMOS at 1MHz without significantly impacting the ICs quiescent current.

Asked differently, what is the circuit for the component show below (taken from the SC192 IC, which switches at 750kHz and has a quiescent current of 50uA).

enter image description here


Update:

I recently found this schematic (from the IR2302 600V NMOS Driver) which shed some interesting light on the matter (annotations assume we are driving a 500V load with a 15V VCC).
enter image description here

To level shift from VCC levels to high voltage levels (say, 500V), they use NMOS pull-downs with resistive pull-ups. This presumably works because the following stage (labeled Pulse-Filter in the diagram below) has very small input capacitance (in the order of a few pF) and so can be switched at high frequency (the part is spec-ed to switch at 1MHz).

When the HV-Level Shifters NMOS are not enabled, the Pulse-Filter only sees +15V on its inputs, which is fine. However, when those NMOS are enabled, the Pulse-Filter sees -500V on its inputs. Presumably, these get clamped, but clamping 500V is no small feat.

The catch with this IC is that it's used to drive N-Channel MOSFETs. For P-Channel MOSFETs, is it as simple as taking the ~Q output of the SR latch on the schematic above (i.e. inverting the output logic)?

\$\endgroup\$
1
\$\begingroup\$

The key is in your above-linked datasheet:

At moderate to heavy loads, the converter operates in the PWM mode with a fixed frequency of 750kHz. At light loads the converter enters the power save mode by modulating the frequency, pulse-frequency-modulation (PFM) which achieves high efficiency under light load conditions.

So it's not really operating at 750kHz and 50uA, more like one or the other. The efficiency starts to drop off below 30mA output current, dramatically so below 10mA.

enter image description here

At 1mA output current, the efficiency is ~69% = Pout/Pin. Pout is 3.3mW so the device is using about 300uA from the 5V line. Still quite remarkable.

\$\endgroup\$
  • \$\begingroup\$ I stand corrected. Thanks for setting me straight. But the verdict is still out as to how the PMOS driver circuit is implemented. I could see a level shifter being used here as the voltages are fairly low, but this doesn't address other drivers that can switch 600V (e.g. IR2302). Maybe there is such a thing as a 600V level shifter, but I'd have to see it to believe it. \$\endgroup\$ – TRISAbits Jul 18 '15 at 4:35
  • \$\begingroup\$ The input voltage of that part is 7V maximum- the gate driver just has to pull the p-channel MOSFET gate down to 0V. The IR bootstrapped drivers actually do have a HV floating well on the chip and HV level shifters- eg. IR2214 1200V! \$\endgroup\$ – Spehro Pefhany Jul 18 '15 at 5:04

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.