2
\$\begingroup\$

I have been trying to find the Absolute value of an integer which is designated to Verilog core using Xilinx C running on Microblaze, what i have seen is that Verilog treats the negative number as a positive number.

I have tried all data types : signed int, int, Xuint32.

My c code is:

signed int data,value;
data=-20;value=0;
putfsl(data,0);
getfsl(value,0);
signed int data1,value1;
data=20;value=0;
putfsl(data1,0);
getfsl(value1,0);

After getting the values of variables I printed them on Hyperterminal.

On my Verilog side the code was:

out <=(in<0)?-in:in;

I also tried this code but results were similar

if(in<0)
   out=-in;
else 
   out=in;

Kindly help me out!

I have also tried other data types and changed parameters but results have not worked out to be I always get the same number I input i.e

in<0

statement is not being true, I also tried in<=0.

\$\endgroup\$
2
\$\begingroup\$

(Disclaimer: I'm not a Verilogger - its signed arithmetic foibles being one of the reasons why not :)

Prior to Verilog-2001 all vector arithmetic in Verilog was unsigned.

In Verilog-2001 you can explicitly call for signed arithmetic, so I think you'll need to cast your in:

if ($signed(in) < 0)
 out = -$signed(in);
else
 out = in;

Reading matter which may be of interest:

Signed arithmetic in Verilog-2001 - Opportunities and Hazards

\$\endgroup\$
  • \$\begingroup\$ Thanks AloT!! It really worked, i had spent like two days solving this very problem.Really appreciate as i had thoroughly searched on the internet, and failed to find any answer. \$\endgroup\$ – aibk01 Aug 11 '11 at 16:08

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.