# process and signal assignment

I have the above code segment. I am a bit confused, so can one help me ?

 wait until rising_edge ( clk ) ;
sig_a <= sig_x and sig_y ;
sig_b <= sig_a ;


Does sig_b use new value of sig_a ?

Both events happen simultaneously, so sig_a gets a new value while sig_b does. In practice this is often done with cascading flip-flops, which are all clocked by the same edge, like in shift registers. This isn't a problem because the delay between the input and the output, so the input will take the old value of the previous output before it changes value.

One of the tricky things about HDL is that assignment statements occur simultaneously. You could re-order the two sig_a and sig_b statements and the result would be the same.

The synthesizer will create two flip-flops for storing both sig_a and sig_b. The output of sig_x AND sig_y will be connected to the data input of the sig_a flip-flop, and the output of the sig_a flip-flop will feed into the data input of the sig_b flip-flop.

As a result, sig_b will store the old value of sig_a on the positive clock edge.

No, sig_b gets the value of sig_a at the start of the process.

<= means "schedule an update to the signal", but it will not be updated until some simulation time passes.

(That amount of time could be 0 ns:

wait until rising_edge ( clk ) ;
sig_a <= sig_x and sig_y ;
wait for 0 ns;
sig_b <= sig_a ; -- sig_b now gets "sig_x and sig_y" from sig_a


But that'll not synthesise...)