Here are some representations of simple VHDL statements.


        Y <= A and B ; 

results in

AND gate symbol


         A <= B or C ;
         D <= A and E ;

results in:

OR gate inputting to AND gate http://www.takeprint.com/wp-content/uploads/2011/01/221.jpg.

What are the representations of the following keywords ?

  • <=
  • :=
  • process
  • entity
  • wait
  • if-then
  • case
  • while
  • for

VHDL is a hardware based language. Thus, all of the keyword must have one representation in real life.

For example, after synthesizing:


what will be the result - just a wire ?

straight line

For a more complex synthesis, what will be the result of

for index in 1 to 32 loop
    if product_register(0) = '1' then
        product_register(63 downto 32) := produce_register(63 downto 32) + multiplicand_register(31 downto 0) ;
    end if ;
    product_register(63 downto 0) := '0' product_register(63 downto 1) ;
end loop ;

When we use for or while, after synthesizing what is the representation?


2 Answers 2


I think you're confused about the nature of VHDL. There isn't a 1-1 mapping between VHDL keywords and gates, rather, most of the keywords you listed are composed of many gates.

The standard logic gates are:

  • NOT
  • AND
  • OR
  • XOR
  • NAND
  • NOR
  • XNOR

There are a few additional structures, such as flip-flops, but the number of basic representations is small. Higher-level abstractions like while and if-else are composed of a large number of these gates, which are themselves composed of a number of transistors. The transistors are the actual hardware, there is no basic electronics component for the symbols you've shown. Everything above the transistors is an abstraction of hardware.

If you're familiar with the architecture of a program in software, what you're asking is very similar to the question "What's the assembly instruction for the class or Array.length keyword?" There is none. Those keywords are compiled to a number of assembly instructions; there's not a 1-1 mapping.

  • \$\begingroup\$ My world only has NAND as a base gate, I guess you must be more cultured. \$\endgroup\$
    – Kortuk
    Commented Aug 11, 2011 at 13:26
  • \$\begingroup\$ No, your word is more pure, so you must be more cultured. Sure, you can build any gates from just NAND or just NOR, but in the real world, it's more efficient to use a few representations. I'm actually over-simplifying, for hand-tuned ASICs there are probably a lot of basic structures. However, I tried to list the ones that would be used in a VHDL simulation. \$\endgroup\$ Commented Aug 11, 2011 at 13:33

To take some questions you've asked in reverse order:

VHDL is a hardware based language.

It's a hardware description language.

Thus, all of the keyword must have one representation in real life.

Not everything you can write in VHDL can be mapped onto real hardware (think access types, which are like pointers). Some of these non-synthesisable bits are very useful for modelling your real hardware in simulations without having to get into low-level nitty gritty like you have to for synthesisable code.

What are the representations of the following keywords ?

Often it depends on context:


A signal assignment - it drives a value onto a signal. If that happens from within a clocked process you get a flipflop as the driver (potentially with some gates feeding its D input). If (as in your examples) you are using it in continuous assignments, you just get the logic gates.


A variable assignment - this creates some logic gates. If you read the variable "above" the assignment in the process, you also get a flipflop.


with a clock signal in the sensitivity list and an if rising_edge(clk) type construct, this can be used to infer flipflops. In synthesisable code I avoid using processes for anything other than clocked logic. In non-synthesisable code, you can use waits and other control flow structures to do behavioural modelling of external hardware.


See this question: VHDL: Component vs Entity


In terms of real hardware, a process with wait until rising_edge(clk) can be used to infer flipflops: http://www.parallelpoints.com/node/69 . In simulation you can wait for a wider variety of things, including simulated time.

if-then case

Some "selection" logic (like a mux for example)

while for

Loops in clocked processes, can be used for various things for example as shorthand to do the same thing to lots of array elements all at once in a single clock cycle.

I have no idea about your last question, the loop you show has an index which is not used within the loop, so it will just be ignored (you're just doing exactly the same thing over and over again)


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