# Pull-down's on CPLD

So I have a Xilinx CoolRunner II CPLD that I'm working with that is talking to conditionally powered peripherals. I'm using the CPLD as a kind of logic level translator between a microcontroller and the peripherals, as well as for some internal logic. I need the peripheral inputs to the CPLD to be low when they're not driven (powered off). My first thought was to use some external pull-downs on I/O lines, but then I read this in one of the manufacture's app-notes:

Avoid pull-down resistors. Always use external pull-up resistors if external termination is required. This is because the CPLD, which includes some I/O driving circuits beyond the input and output buffers, may have contention with external pull-down resistors, and, consequently, the I/O will not switch as expected.

and elsewhere they recommend:

Avoid pull-down resistors on pins. All Xilinx CPLDs include additional circuitry on an I/O pin beyond just the I/O buffer. This includes ESD as well as circuits that manage power up behavior. For example:

1. XC9500 has High-Z during power on
2. XC9500XL/XV has High-Z during power on, then a keeper latch
3. XPLA3 has High-Z during power on, then a keeper “half latch”
4. CoolRunner-II has High-Z during power on, then a keeper latch

Pull-down resistors “fight” the internal pin electronics, which may misbehave due to the external pull-down. For the most predictable behavior, avoid pin pull-down resistors.

I'm currently pursuing if I can use the peripheral's power signal as an indication to pull the line low or let it be driven by the peripheral, so I'll do that if possible. My question is what would happen if I disregard the manufacturers' warning? What if I use an extremely weak pull-down? 10Meg? 100Meg? Has anyone ever done this?

If your pull-down is 1M$\Omega$ then anything above 10M$\Omega$ (rule-of-thumb) can be considered as a weal pull-up, that means a 1:10 ratio. It means that having both on a 3.3V system the input will be at 0.3V.