I've just started using Quartus to synthesize a VHDL design that I created a while ago. Inside of this design are things like DFFs, decoders, etc. I noticed that Altera has IP of its own with the same functionality.

Are there any significant benefits to using the Altera IP? I would rather not uproot all of my VHDL files but if there are significant size/performance enhancements then I might consider it.


For primitives, absolutely no benefit performance wise. The only use is it means you don't need to create files with your own primitives in, but if you rely on the Altera ones then migrating to something from another manufacturer would be harder.

Some things like FIFOs may contain Altera specific inline timing constraints or other synthesis directives for example that may make life easier in the long term, but its nothing you couldn't do in your own files, and it probably wont help much in terms of performance.

The bits where it gets interesting are for inferring hardware specific stuff like DSP blocks, Block RAM, Transceivers, IO Buffers, etc. These can be quite useful to ensure you get the hardware you want and not leave it to chance that the synthesiser will infer the correct thing. But to be honest if you follow the design templates (click the button that looks like a scroll in the Quartus HDL editor to see them), then this can all be inferred quite successfully.

It's worth noting that I am ignoring the more complex stuff that can be generated from MegaWizard (I think the renamed that!) or Qsys. These can be very useful - from stuff like PLLs all the way up to PCIe cores, DDR controllers etc. These are useful for the obvious reasons (the why reinvent the wheel reasons).

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  • \$\begingroup\$ This is exactly what I was looking for. Thank you! \$\endgroup\$ – Ted X Jul 20 '15 at 20:02

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