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The package contains the following lines:

file INPUT: TEXT is in “STD_INPUT”; file OUTPUT: TEXT is out “STD_OUTPUT”;

For some reason these remind me of the standard input and output streams from my C language lessons. What do these mean here? Is it really possible to read/write the standard input/output stream by using this package? How?

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  • \$\begingroup\$ You'll find vendors near universally tell you "STD_INPUT is a file_logical_name that refers to characters that are entered interactively from the keyboard, and STD_OUTPUT refers to text that is displayed on the screen." These happen to correspond to stdin and stdout. You READ or READLINE from INPUT (STD_INPUT) or WRITE or WRITELINE to OUTPUT (STD_OUTPUT). File I/O is host system implementation dependent. \$\endgroup\$
    – user8352
    Commented Jul 21, 2015 at 0:56
  • \$\begingroup\$ No, what I mean to ask is, standard input and output streams are not about file IO where we create a "handle" to a file on some sort of media and then do sequential or random read/write access to its sectors. Standard input stream comes from the keyboard and is built up of characters. The standard output stream is the PC screen. I don't think that VHDL means this when it says STD_INPUT and STD_OUTPUT or am I misunderstanding something? \$\endgroup\$
    – quantum231
    Commented Jul 21, 2015 at 23:56
  • \$\begingroup\$ Actually, how you access file contents in VHDL comes from UNIX/C. You however don't have the ability to seek, ctermid, freopen, etc. VHDL is a hardware description language not a general purpose programming language. \$\endgroup\$
    – user8352
    Commented Jul 22, 2015 at 1:31

2 Answers 2

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Short answer: Yes :)

Unfortunately not every simulator supports it.

Currently, I know only GHDL and ModelSim / QuestaSim. I have no info on iSim or xSim.

I don't know any synthesis tool which supports STD_IN and STD_OUT. Xilinx XST has file I/O support but I think no support for STD_IN/STD_OUT.

Vivado has no file I/O support and Quartus does not support std.textio.

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  • 1
    \$\begingroup\$ File operations are host implementation dependent and no textio is supported for synthesis while file I/O may be supported for object initialization (default values) during elaboration, some synthesis vendors superimposing their own initialization regime on supported constructs (both QuartusII and ISE). Support for textio during simulation is required for compliance with the VHDL standard. \$\endgroup\$
    – user8352
    Commented Jul 21, 2015 at 0:56
  • \$\begingroup\$ I only used QuestaSim/ModelSim. \$\endgroup\$
    – quantum231
    Commented Jul 21, 2015 at 23:56
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Minimal examples tested on GHDL 0.33

Read 4 input lines from stdin, and spit each one right back to stdout:

library std;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;

entity tmp_tb is
end;

architecture behav of tmp_tb is
begin
    process
        variable my_line : line;
    begin
        for i in 3 downto 0 loop
            readline(input, my_line);
            writeline(output, my_line);
        end loop;
        wait;
    end process;
end;

Read 4 integers from stdin and write them to a a signal. This can then be observed on a generated wave file. Uses: https://stackoverflow.com/questions/7271092/vhdl-convert-string-to-integer-best-way

architecture behav of tmp_tb is
    constant clk_period : time := 1 ns;
    signal my_integer : integer;
begin
    process
        variable my_line : line;
        variable my_integer_var : integer;
    begin
        for i in 3 downto 0 loop
            readline(input, my_line);
            read(my_line, my_integer_var);
            my_integer <= my_integer_var;
            wait for clk_period / 2;
        end loop;
        wait;
    end process;
end;

A bunch of stdout write examples on GitHub: https://github.com/cirosantilli/vhdl-cheat/blob/3721d42a1f1a8d3de3462ac70f90374c910f176e/write_tb.vhdl

Write integer as hex to stdout: https://stackoverflow.com/questions/37879954/how-to-write-an-integer-to-stdout-as-hexadecimal-in-vhdl

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