VHDL: What does STD_INPUT and STD_OUTPUT appearing in std.textio mean?

Question

The package contains the following lines:

file INPUT: TEXT is in “STD_INPUT”; file OUTPUT: TEXT is out “STD_OUTPUT”;

For some reason these remind me of the standard input and output streams from my C language lessons. What do these mean here? Is it really possible to read/write the standard input/output stream by using this package? How?

Answer 1

Short answer: Yes :)

Unfortunately not every simulator supports it.

Currently, I know only GHDL and ModelSim / QuestaSim. I have no info on iSim or xSim.

I don't know any synthesis tool which supports STD_IN and STD_OUT. Xilinx XST has file I/O support but I think no support for STD_IN/STD_OUT.

Vivado has no file I/O support and Quartus does not support std.textio.

Answer 2

Minimal examples tested on GHDL 0.33

Read 4 input lines from stdin, and spit each one right back to stdout:

library std;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;

entity tmp_tb is
end;

architecture behav of tmp_tb is
begin
    process
        variable my_line : line;
    begin
        for i in 3 downto 0 loop
            readline(input, my_line);
            writeline(output, my_line);
        end loop;
        wait;
    end process;
end;

Read 4 integers from stdin and write them to a a signal. This can then be observed on a generated wave file. Uses: https://stackoverflow.com/questions/7271092/vhdl-convert-string-to-integer-best-way

architecture behav of tmp_tb is
    constant clk_period : time := 1 ns;
    signal my_integer : integer;
begin
    process
        variable my_line : line;
        variable my_integer_var : integer;
    begin
        for i in 3 downto 0 loop
            readline(input, my_line);
            read(my_line, my_integer_var);
            my_integer <= my_integer_var;
            wait for clk_period / 2;
        end loop;
        wait;
    end process;
end;

A bunch of stdout write examples on GitHub: https://github.com/cirosantilli/vhdl-cheat/blob/3721d42a1f1a8d3de3462ac70f90374c910f176e/write_tb.vhdl

Write integer as hex to stdout: https://stackoverflow.com/questions/37879954/how-to-write-an-integer-to-stdout-as-hexadecimal-in-vhdl