I have a couple of questions. In the diagram below, when the current falls to 0 , the NMOS is supposed to turn off. Similarly when the voltage error increase the PMOS turns off. However in the diagram both the signals are given to a driver. What is this driver component and how d it decide which signal to send out? How should I implement it in terms of transistors? The picture is taken from 
This is the problem with developing a real-world circuit from a "simplified" block diagram. There are no component values, the circuit connections are representative only and may not show much more than the direction a sign is going. The assumption is you will select the specific devices to use and determine the connections to be made.
In general, a MOS driver output is connected to the FET at the gate and referenced to the source connection. The drawing looks a bit suspicious to me and I would suggest you need two drivers or a single driver and two gate transformers with isolation.
One of the other problems I see in this diagram is the zero-current detector. The comparator is simply not connected to two points where current can be measured. I would expect a small value resistor or shunt on the return leg from the ground symbol and the comparator connected to each side of the resistor.
Can you let us know this source of this drawing?
thanks, Doug
Certainly,
Here is a quick sketch I just made and it is as simplified as your original, maybe more so. It is one way I have typically driven MOS FETs in the past. Note, the transformer is usually a very small ferrite type. 
