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I have a couple of questions. In the diagram below, when the current falls to 0 , the NMOS is supposed to turn off. Similarly when the voltage error increase the PMOS turns off. However in the diagram both the signals are given to a driver. What is this driver component and how d it decide which signal to send out? How should I implement it in terms of transistors? The picture is taken from enter image description here

enter image description here

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This is the problem with developing a real-world circuit from a "simplified" block diagram. There are no component values, the circuit connections are representative only and may not show much more than the direction a sign is going. The assumption is you will select the specific devices to use and determine the connections to be made.

In general, a MOS driver output is connected to the FET at the gate and referenced to the source connection. The drawing looks a bit suspicious to me and I would suggest you need two drivers or a single driver and two gate transformers with isolation.

One of the other problems I see in this diagram is the zero-current detector. The comparator is simply not connected to two points where current can be measured. I would expect a small value resistor or shunt on the return leg from the ground symbol and the comparator connected to each side of the resistor.

Can you let us know this source of this drawing?

thanks, Doug

Certainly,

Here is a quick sketch I just made and it is as simplified as your original, maybe more so. It is one way I have typically driven MOS FETs in the past. Note, the transformer is usually a very small ferrite type. gate driver and transformer

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  • \$\begingroup\$ I have it on my PC. Right now I am unable to pin point where I got it from. Could you add a diagram of how the gate driver is supposed to look. At this point I am a little confused. \$\endgroup\$ Jul 21 '15 at 3:07
  • \$\begingroup\$ Is this your source of information? See figure 4.10. [link](liu.diva-portal.org/smash/get/diva2:546843/FULLTEXT01.pdf) \$\endgroup\$
    – dougp01
    Jul 21 '15 at 3:40
  • \$\begingroup\$ Yep. That is the one \$\endgroup\$ Jul 21 '15 at 4:01
  • \$\begingroup\$ I am a little confused. The input to the comparator are the 2 lines coming from zero current and the latch. Why is there a ferrite transformer? Is this for isolation. Also for a MOSFET to be used as a switch it should be in linear regions. Why do you connect the source and gate of the NMOS device? \$\endgroup\$ Jul 21 '15 at 6:16

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