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Board: Tiva™ C Series TM4C1294

EK-TM4C1294XL

My program is listening to 2 UART ports (UART 3 and 7)

I've encounter a problem that I'm losing some bytes received and I'm suspecting that this issue relate to the UART's interrupts.

I understand that UARTs have nested interrupts but does both of them are serial?

For example: I'm inside UART 3 interrupt function and then while UART 3 didn't finish the interrupt (just copy their bytes to buffer) UART 7 interrupts arrives, does the system moves to UART 7 or it will first finish UART 3 and then moves to the UART 7?

Currently I'm suffering from error bytes something like 45-400 bytes for file that his size in 12 Mbytes.

I'm suspecting the above issue cause this issues.

p.s if only 1 UART is sending data I have binary same files on both host and PC.

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  • \$\begingroup\$ You need to set priority, also 45-400 bytes on a 12 Mb isn't a disaster, you can calculate the ratio on byte loss per millions. With any comm protocol, you will loose some info. \$\endgroup\$ – MathieuL Jul 22 '15 at 14:48
  • \$\begingroup\$ What API are you using? \$\endgroup\$ – MathieuL Jul 22 '15 at 14:51
  • \$\begingroup\$ Also, What devices are sending data to the MCU? \$\endgroup\$ – MathieuL Jul 22 '15 at 14:53
  • \$\begingroup\$ You send data to your PC on 2 UART channel? \$\endgroup\$ – MathieuL Jul 22 '15 at 14:54
  • \$\begingroup\$ i am using usb to ttl to send the info to the rx of the micro chip uart pins... \$\endgroup\$ – MrLevy Jul 22 '15 at 17:21
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Your problem will be solved if you give priority levels to your interrupts, so first won't bother second.

Here is one example:

NVIC_SetPriority(UART3_IRQn, 0);
NVIC_SetPriority(UART7_IRQn, 1);

While one interrupt is being serviced, second arrived is in pending state.

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  • \$\begingroup\$ But in case I have few interrupts it will serve them as fifo? \$\endgroup\$ – MrLevy Jul 22 '15 at 14:02
  • \$\begingroup\$ Please be more clear. \$\endgroup\$ – Junior Jul 22 '15 at 14:04
  • \$\begingroup\$ For example uart 3 will have interrupt then 7 then 3 .does the priority won't starve com7? \$\endgroup\$ – MrLevy Jul 22 '15 at 14:12
  • \$\begingroup\$ And priority 1 is higher than 0? \$\endgroup\$ – MrLevy Jul 22 '15 at 14:13
  • \$\begingroup\$ Lower priority numbers represent higher priority level. \$\endgroup\$ – Junior Jul 22 '15 at 14:15
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The solution I would implement is a uDMA. When the interrupt is raise, you let the uDMA handle the transfer therefore you can transfer data in the 2 uart at the same time tm4c129 can support up to 32 uDMA channels.

There is a uDMA example that is given by ti in tivaware. But with out any information about your device I cannot tell much more.

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Each interrupt handler will run to completion before the other one gets any CPU cycles. If you change the interrupt priorities, that will no longer be true. In the case of Tiva UARTS, you'll want to adjust FIFO thresh-holds such that one UART can't overflow while you are servicing the other one. If both UART FIFOs fill up at the same time, you will drop some characters.

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