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Please, explain me the CMOS Inverter at the physical layer trying not to involve mathematical formulas. Just in terms of physics. Mostly I wonder how the same high voltage on the gates can cause the nMOSFET to conduct and the pMOSFET to not conduct? My guess was that NMOS is in an enhancement mode and PMOS is in a depletion mode. But I know it is wrong.

enter image description here

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  • \$\begingroup\$ You need to show a schematic to give anything to discuss \$\endgroup\$ – Kevin White Jul 22 '15 at 20:25
  • \$\begingroup\$ @Alex Ho: I added a diagramm of a CMOS inverter. I assume this is what you meant. \$\endgroup\$ – Curd Jul 22 '15 at 21:12
  • \$\begingroup\$ @KevinWhite How is a schematic going to help, if the question is about physics of CMOS gates? \$\endgroup\$ – Dmitry Grigoryev Dec 15 '15 at 10:59
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No, in CMOS both, the N-channel and the P-channel MOSFET are enhancement types.

The N-channel is enhanced by positive voltage at the gate with respect to its source.
The P-channel, however, is enhanced by negative voltage at the gate with respect to its source.

Thus

  • a H at the input turns on the N-channel MOSFET (positive voltage between its gate and source) and turns off the P-channel MOSFET (0V between its gate and source) and
  • a L at the input turns off the N-channel MOSFET (0V between its gate and source) and turns on the P-channel MOSFET (negative voltage between its gate and source).
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Take a closer look at the PMOSFET. Notice something different from the NMOSFET?

...

That's right, the source is tied high. Since VGS of the PMOSFET needs to go more negative in order to turn it on, it will be on when the NMOSFET is off and vice versa.

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I'm a little confuse about your question; you want a physical explanation, but you write a circuit! So there are two different level of abstraction: physic (low) and circuit (high) levels. So, let me make some assumption of your knowledge, and of course ask for explanation if my assumptions are incorect.

  • First of al... I assume you are seeking for the link between the two. In particular, because you have asked for CMOS, I assume you want to know about the physic advantage for using the combination of N-MOS and P-MOS, and also I assume you know how physically work the NMOS and PMOS, so you well know you can consider the NMOS and PMOS as "switch": for NMOS, when Vgs is "high" the current can flow from source to drain, when Vgs is "low" it cannot; viceversa for PMOS when Vgs is "high" the current cannot flow from source to drain, if Vgs is "low" it can. So, let starting.

  • The CMOS bheavior for inverter gate From the previous explanation, because the input is connected both to NMOS and PMOS gate, you well understand that only one of the two devices can conduce. If the input is "high", the PMOS (pull up) is disconnected, and NMOS is ON so the output is directly connected to GND ("low" level). Viceversa, if the input is "low" level, the NMOS (pull down) is disconnected and PMOS is ON so the output is directly connected to Vdd ("high" level). This is bheavior of an inverter. For a more detailed discussion, note that for the input I used "high" and "low" but not Vdd and GND rispectvely. This because the voltage at gate of the NMOS and PMOS can be lower than Vdd (for NMOS) or higher than GND (for PMOS) and the bheavior doesn't change. This is the "regenerative" bheavior, and is extremely usefull because the input of this CMOS is the oput of a previous stage, but the signal have travelled trough a resistive interconnection that have degraded its level. In other hand, if the voltage is too lower than Vdd or too higher than GND, the NMOS and PMOS works either in the active zone (they bheave as a resistors). This is a extremely unwanted situation because there is a direct path from Vdd to GND and we have a static power consumption, that I will described in the next section.

  • The static power consumption problem The use of the CMOS structure is strongly linked to static power consumption problem. Indeed, you can imagine a more simple structure that have the inverter bheavior, but use only one MOS (NMOS or PMOS). For example, in your circuits you can replace the PMOS with a resistor R; the output is located as in figure, between the R and the drain of NMOS. It is very simple to explain the inverter behavior: if the input of NMOS is low, the NMOS is off and so the output is high ( Vdd ) because there is no current and then no voltage drop on R. If the input is high, the NMOS is a short circuit that connect the output to GND. In this case, you can see a direct current path from Vdd to GND trough R. This current produce a static power consumption, "static" because is present even when the signal is stationary. When you use the CMOS, there isn't static power consumption: there isn't a direct path from Vdd to GND because NMOS and PMOS are not ever ON simultaneously. There is only a little dinamic power consumption because, during the transition of the signal, for a small amout of time, PMOS and NMOS are in linear region simultaneosuly and then there is a direct path from Vdd to GND. The reduction of the static power consuption is a main topic in the integrated circuit design.

  • Deep inside the logic bheavior If you want to understand better the CMOS inverter, you shouldn't consider ONE CMOS inverter! This is because in the logic network there is "inverter chain". All logic gate (AND, OR ecc) is obtained starting from CMOS inverter, with few modification (adding one NMOS or PMOS). Because every logical circuite is composed by a cascade of logical gates, you can consider the general case of a in inverter that drives another one. For example, previolusly I talk about the static power consumpation. If you take a CMOS inverter, and put a resistor on output, of course you have a static power consumption, but the circuite you have realized is useless. If you put another CMOS inverter at the output, the static power consumption is still zero because the gate of CMOS don't absorbe current. Even this circuite, in this way, is useless (two inverter in cascade) but you have to imagine this is only a subset, for Learning pourpose, of a more complex situation, because as I said the other logic gate are modifications of the CMOS inverter.

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    \$\begingroup\$ Please consider the use of paragraphs (a distinct section of a piece of writing, usually dealing with a single theme and indicated by a new line, indentation, or numbering) to make your answer readable. \$\endgroup\$ – Transistor Dec 15 '15 at 11:26
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CMOS inverters can also be used as linear amplifiers. In this case, the device is biased at the input with a dc voltage of app. at 50% of the supply voltage. Then, the upper transistor acts as a high-resistive load resistance. This can be easily verified using the output characteristics of both units in a common diagram, see here:

http://gram.eng.uci.edu/~ece151/ece151/slides1/sld030.htm

A corresponding transfer curve input-output can be seen here:

http://gram.eng.uci.edu/~ece151/ece151/slides1/sld031.htm

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Normally when the gate voltage is negative with respect to source a PMOS turns ON or we can say current flows from source to drain if Vds is applied.The same is true for NMOS when the gate voltage is positive with respect to source terminal.Considering the circuit of an inverter when the input is logic 1,NMOS turns ON and PMOS is OFF.Thus the output line gets connected to GND which is normally 0V for digital circuits.When input is logic 0,PMOS turns ON and NMOS turns OFF.Thus the output line gets connected to VDD which is +5V for digital circuits.The advantage of this circuit is that CMOS circuits consume power only when they are switched.

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