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I have a short UCF file with the following content:

## Fan Control
## =============================================================================
##  Bank:               15
##      VCCO:           1.8V (VCC1V8_FPGA)
##  Location:           J48, Q1
## -----------------------------------------------------------------------------
NET "FanControl_PWM"    LOC = "BA37";           ## Q1.Gate; external 1k pullup resistor
NET "FanControl_Tacho"  LOC = "BB37";           ## J48.3; voltage limited by D2 (DDZ9678 - 1.8V zener-diode)
NET "FanControl_*"      IOSTANDARD = LVCMOS18;

# Ignore timings on async I/O pins
NET "FanControl_*"      TIG;

This file bounds two physical pins to two top-level ports. Additionally, the I/O standard is set to low-voltage CMOS 1.8 V, because bank 15 is sourced with 1.8 V.

To reduce warnings in Xilinx ISE (trace) I specified that all timing paths to and from these pins should be ignored (timing ignore -> TIG).

Question:

  • How can I translate TIG into Vivado's XDC syntax?

What I discovered so far:

  • set_false_path is only for internal paths and
  • set_disable_timing seams to be very special
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set_false_path is not only for for internal paths.

You can use set_false_path for

The port from which all paths are to be set as false paths:

set_false_path -from [get_ports ]

set_false_path -to [get_pins {}]
set_false_path -through  [get_pins {}]
set_false_path -from  [get_pins {}]

set_false_path -from [get_cells <>] -to [get_cells <>]

If you want to set all paths between two clock domains:

set_false_path -from [get_clocks ] -to [get_clocks ]

Because you want to set false paths from i/o ports,use

set_false_path -from [get_ports FanControl_PWM]
set_false_path -from [get_ports FanControl_Tacho]
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  • \$\begingroup\$ Ok, set_false_path -from [get_ports ...] works for inputs, but Vivado complains about set_false_path -to [get_ports ...]. Or should I use get_pins? \$\endgroup\$ – Paebbels Jul 23 '15 at 19:23
  • \$\begingroup\$ Which paths do you want to set as false path ? All paths from a specific i/o port ? or some internal nets ? \$\endgroup\$ – rahdirs Jul 24 '15 at 16:22
  • \$\begingroup\$ I want to set all low-speed GPIO pins as false path, because no timing is known for push buttons or LEDs. Currently this is done by TIG in both ways. The nets behind the pads are all registered. So a double FF input synchronizer for e.g. buttons and an output register for e.g. LEDs. Do I need to set the false path between the output of the IOB register and the OPAD? \$\endgroup\$ – Paebbels Jul 24 '15 at 18:27
  • \$\begingroup\$ Regarding your last example: PWM is the output to the fan transistor and Tacho is the tacho/speedometer signal from the fan to the FPGA. \$\endgroup\$ – Paebbels Jul 24 '15 at 18:31
  • \$\begingroup\$ What does it complain about set_false_path -to [get_ports] ? \$\endgroup\$ – rahdirs Jul 25 '15 at 9:26

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