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I am routing a PCB with MOSFETs in LFPAK (aka SOT-669, Power SO8) packages for the 1st time. They look like D2PAK. The manufacturer, NXP, advises to draw identical polygons on top and bottom sides, connected to the drain tab, and linked together by vias, to transfer the heat from top to bottom side (bottom side cooling). They suggest to put the vias right through the drain pad, and around it.

Vias

They mention vias with 0.8mm (32 mils) hole diameter, but they don't comment on how they came up to this value. Isn't it too big ? I am concerned about the solder paste filling all the vias and the MOSFET not being soldered well. I'll have them soldered in an oven.

My reference : https://assets.nexperia.com/documents/application-note/AN10874.pdf, page 16.

Polygon connect

Should I use thermal relieves to connect the MOSFETs to the polygons ? I've read I shouldn't use them for vias.

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  • \$\begingroup\$ Are you sure they dont talk about filled vias? \$\endgroup\$ – PlasmaHH Jul 24 '15 at 10:16
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No, don't use thermal relief vias. The reason they are that large is so that they WILL fill up with solder, that will make a strong heat connection to the other side of the PCB. I have done several PCB's using this method, and it works well, the MOSFETS will solder just fine.

The PDF used 1 oz for its simulation, which usually is 1/2oz base and 1/2 oz plate. I would recommend using at least 2 oz copper, (1oz base, 1oz plate) if you have other smaller SMT parts on the board, or a heavier plating if just the MOSFETs. If you can get 3oz or 4oz, you will have a much better heatsink.

Look on page 17 of that PDF, more holes used to link the layers the cooler the MOSFETS ran because they had better thermal connection to the other layers of PCB.

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  • \$\begingroup\$ What's interesting is that 54 vias has a smaller temperature than 63 vias (page 17). Anyone know the reason of what could cause that ? \$\endgroup\$ – efox29 Nov 4 '15 at 3:10
  • \$\begingroup\$ Thermal-dynamics is a strange beast IMHO. I would assume that the placement of the holes might affect performance, if the holes got the same amount of solder squeegeed in, how well the plating process in the holes worked, etc. The main fact is that just with a few vias linking the two sides, the junction temperature decreased \$\endgroup\$ – David Drysdale Nov 4 '15 at 20:21
  • \$\begingroup\$ I finally used 0.3mm (12 mil) thermal vias. I had the components mounted by reflow soldering. Some of the soldering paste went through the board, but moderately. The components seem to be soldered well, although I didn't have the chance to test the boards yet. I didn't use thermal relief connections to maximize heat transfer and current throughput, and because they are totally useless with reflow soldering, as the whole PCB is heated. \$\endgroup\$ – dplamp Nov 5 '15 at 7:50
  • \$\begingroup\$ In the meantime, I tested the board that has a 4-layer stack-up, and it works pretty well. \$\endgroup\$ – dplamp Dec 22 '16 at 13:32
  • \$\begingroup\$ efox29: it's such a small change. I think it is not significant. You can tell from the trend of the plot. The actual soldering process adds much more uncertainty on the thermal resistance. \$\endgroup\$ – dplamp Jan 16 at 7:47

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