# LTSpice's ltline (lossy transmission line) symbol slowing down the simulation process. What can I do?

LTSpice has the element called Lossy transmission line (symbol name ltline):

I tried to simalate a pretty simple schematic:

• R2,R3 and R4 resistors are for solve floating node problem.

Simulation of this scheme is extremely slow (about 30us/sec). If I remove the ltline symbols and replace them with a wire or a resistor the simulation speed is a link of an eye!

However I need an element representing an electrical wire. Is there any solution?

Thanks!

UPDATE 1

After making the simulation times shorter (1ms) I received some kind of a result:

And I make a note that if the O1 line becomes shorter the simulation time rises.

• What actual system are you trying to simulat? – The Photon Jul 24 '15 at 18:43
• @ThePhoton I tried to simulate the signal transmission over the power line. The signal source is a V2 connected to the line via C1 cap. The signl is measured at the top end of the R1 load resistor. – Roman Matveev Jul 24 '15 at 18:46
• What is your unit of distance? The transmission line model in LTSPICE is probably meant to represent a signal line, not a power line. If your lengths are less than 1/10 of a wavelength (so less than about 60 km), I would think that just using a single lumped RLC model instead of the LTRA elemenat should get you a close-enough solution. – The Photon Jul 24 '15 at 18:51
• @ThePhoton So is that correct that I should put R and L in a seria on the "top" line wire? And where should I put the cap? between R and L? – Roman Matveev Jul 24 '15 at 18:56
• Please follow ecircuitcenter.com/Circuits/tline1/tline1.htm It gives better simulation speed for transmission line. – user90816 Nov 4 '15 at 13:02

Simulating a transmission line is hard!

The Spice model used will be a very long array of RLC lumped elements to simulated the basic model of a transmission line. With so many elements to simulate it will take a long time. Removing the transmission line will in turn remove all the many elements and so it will speed up.

• I tried to make the simulation time mush shorter (let's say - 1ms) and I make a note that the longer the line the shorter the simulation time. So fo 1 km of wire it took 10 seconds to simulate the trace, with 1m - couple of minutes. – Roman Matveev Jul 24 '15 at 18:45
• @TomCarpenter I would be surprised if a modern SPICE implementation used a long RLC network to simulate transmission lines. A much better solution if you don't care about the actual state inside the transmission line is to use a 2-port network which captures the solution to the telegrapher's equation: see here – helloworld922 Jul 24 '15 at 19:14
• @helloworld922 As far as I remember when playing with LTSpice it uses an RLC ladder. If someone knows for definite please do correc me. A 2-port approach would be better but I don't recall LTSpice being that complex. – Tom Carpenter Jul 24 '15 at 19:23

The telegrapher equations do not capture the actual delay in the propagation down the line. They only capture phase and loss. The typical two port model of a transmission line does this as well. As a result, this typical model is only good for steady state simulations.

Said a different way, real transmission lines have memory while simple two port models do not.

• Incorrect. The Telegrapher’s equations do capture the delay, since they reduce to two Helmholtz (wave) equations about the current and the voltage. – user110971 Jul 10 '19 at 18:01

My apologies for the necromancy, but the reason why the simulation goes slow is because of the delays of the transmission lines compared to the simulation time: ~14.5ns and ~1.45us, out of which the smallest one will cause the slowest simulation timestep. The internal models have nothing to do with this. The same crawl would happen if the lossy transmmission lines (ltline) would be replaced by (roughly) equivalent ideal transmission lines (tline). The solution for this (seeing the value of the input source) is what @ThePhoton mentions in OP's comment.