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I'm a newbie at electronics and this question has kept me occupied for a while:

How do electrical signals not get out of sync in integrated circuits and CPUs?

For example, let's take a look at 3 bit adder:

http://www.visionics.a.se/html/curriculum/Experiments/Full%20Adder/Images%5CImage162.gif

As you can see, signal from "C" going the bottom path goes through just one logic element, however signal from "A" has to go through at least 2 or 3 logic elements.

Wouldn't the signal "A" get delayed? What if one signal goes through no logic elements, and the other has to go through 100,000? How do they get synchronized? How does CPU make sure right ones and zeros get processed at the right time?

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This is why there is clock. Indeed sometimes there is unstable output on logic circuits like adders, but the output is only registered on clock strobe, so the time to stabilize is known. This is exactly why you can't run with clock frequency higher than specified- signals will not get on time yo inputs.

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  • \$\begingroup\$ Thanks. I've heard of clock but I'm not sure how it exactly helps with synchronization though. Could you go in more details. I also have a follow up question about what happens if synchronization takes more than 1 clock cycle? That is possible, isn't it? One signal goes directly to input, the other has to go through many gates that take 1.1 cycle. \$\endgroup\$ – bodacydo Jul 25 '15 at 6:51
  • \$\begingroup\$ Are you studying electronics now? I think it's better to learn that is class. Just imagine there is a d-flip-flop, a thing that has one input and one output. Output becomes equal to input when clock rises high, and then remains stable until the next clock. So what did not come in time will not be registered. That's it. \$\endgroup\$ – Gregory Kornblum Jul 25 '15 at 6:58
  • \$\begingroup\$ Thanks. I'm not studying electronics and have very little understanding of it. It's just question that has been on my mind as a programmer. So the chip designers have to make sure no signal gets delayed for too long in some more complicated circuit, else it will not get registered? \$\endgroup\$ – bodacydo Jul 25 '15 at 7:30
  • \$\begingroup\$ Oh, yes. In fact this is one of the hardest challenges both in logic and physical design of the chip. Same challenge is present in FPGA design, but as almost any electronics engineers code VHDL, sometime you can see designs that can't run even 10MHz on modern hardware. \$\endgroup\$ – Gregory Kornblum Jul 25 '15 at 7:35
  • \$\begingroup\$ What about Intel CPUs that run at 4Ghz? Are they all hand drawn? There are 10 billion transistors. How did they get it all so right that it never locks up due to delays. \$\endgroup\$ – bodacydo Jul 25 '15 at 8:33

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