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We have designed quite a few FPGA-based boards, and so far, we have used a lot of bypass capacitors. Our rule of thumb was, "as many as we can".

In our next design, we would like to reduce the part count. Since BGA packages are quite dense, the distance between several supply pins (say for the 1.2V VccInt rail) are quite small (<1cm in most cases).

Would it make sense to replace 4 100nf capacitors for 4 supply pins with a single, larger bypass capacitor, located such that it is as equidistant to the 4 pins as possible?

EDIT: Here's the source of my confusion: Xilinx has a PCB design guide for Spartan 6 devices here. For example, if you look at Table 2.1 on page 14, for an LX45 device with FGG484 package, for the VccInt rail, it recommends a total of 1 100uF, 1 4.7uf and 2 0.47uf capacitors. The thing is, this device has 20 VccInt pins!. Is it really recommending using 2 0.47uf capacitors for 20 pins?

To add to the confusion, Xilinx's own evaluation board for the same device has 6 2.2uf, 5 10uf, and 1 470uf capacitors for the same 1.2V VccInt rail!

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    \$\begingroup\$ replacing 4 100nf caps with 1 400nf cap would completely change the frequency response of the decoupling due to a shift in the SRF. \$\endgroup\$ – Mark Aug 13 '11 at 20:10
  • \$\begingroup\$ That's true. The source of my confusion is a Xilinx document (pcb design guidelines for Spartan6). I'll edit the question and clarify. \$\endgroup\$ – SomethingBetter Aug 13 '11 at 20:41
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  1. Apart from the capacitors, don't forget the planes. See p. 25 of the referenced documentation. They are depending on that instead of 0.1 uF (100 nF) at 0.01 uF (10 nF) caps.
  2. The bulk capacitors depend on maximum current and maximum current step. Use the XPE (Xilinx Power Estimator) (S6 link) to get a handle on that.
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  • \$\begingroup\$ So do you read their recommendations the same way that I read them: 2 0.47uf capacitors for 20 VccInt pins? \$\endgroup\$ – SomethingBetter Aug 15 '11 at 7:47
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It would be best to follow the FPGA manufacturer's recommendations for decoupling capacitors and board layout.

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    \$\begingroup\$ This is the right answer. The FPGA vendors go through many boards and experiments to get this right for you. They are also aware of part count being a critical consideration of their customers, so that's probably seriously being taken into account. If you're going to do anything "exotic", at the least simulate it. \$\endgroup\$ – Saar Drimer Aug 13 '11 at 18:31
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    \$\begingroup\$ Yes, but their own recommendations aren't clear as well. Their own eval boards and recommendations don't agree with each other. I've edited the question to show an example. \$\endgroup\$ – SomethingBetter Aug 13 '11 at 20:49
  • \$\begingroup\$ To expand on @Leon Heller's suggestion, start with that but don't end there. Since FPGA current is so very frequency dependent (unlike a processor or DRAM). \$\endgroup\$ – Brian Carlton Aug 13 '11 at 23:50

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