# Nesting entities in VHDL (Altera Quartus)

I want to ask a question. I'm trying to simulate a cpu. I did my schema and basically there are two logical parts of the CPU.

The first part is composed of a FIFO buffer, Cache memory for instructions and a PC register.

I created architecture and entities for each of the 3 named elements.

Can I make one entity that contains all of these 3 entities and their architectures? I'm stubmbled on how to do that, and I would appreciate any help you can provide ;)

EDIT: I found this tutorial http://vhdlguru.blogspot.com/2010/03/entity-instantiation-easy-way-of-port.html

It's rather useful, but I'm interested, if I have entities ab, ac, ad and one top entity in which I want to instate those entities.

If I want to map ports of entity ab to ad entity ports, how should the code look like:

HA1 : entity work.ad port map(
out2 => InstCacheIn1,
out2 => InstCacheIn2,
sum => s1,
carry => c1
);


How to explicitly tell that out1, out2 are ports of entity ab, and I want to map them to ports InstCacheIn1 and InstCacheIn2 of entity ad?