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After synthesis of my verilog code. I am getting the below timing report. I think it showing any mistake in my code.

Timing Summary:

Speed Grade: -2

Minimum period: 2.334ns (Maximum Frequency: 428.376MHz)
Minimum input arrival time before clock: No path found
Maximum output required time after clock: 1.282ns
Maximum combinational path delay: No path found

The main thing which bother me is the comment highlighted by bold. Is it showing of any kind of error?

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No it's no error.

Synthesis just estimates timings because you didn't apply any constraint file. In the normal ISE flow, constraints are applied in the translate step. If this is to late and you need earlier constraint checks or optimizations, then you can apply a XST constraint file (*.xcf) with timing information.

The syntax is the same as in ucf files but only timing constraints are allowed. The processing of an xcf file can be enabled in the synthesis process properties.

Edit:

Sorry I overlooked your bold lines as I wrote my answer.

There are 4 types of connections in a design (in order of your reported lines):

  • clocked element to another clocked element (e.g. flip flop)
  • Input pin to clocked element
  • clocked element to output pin
  • Input pin to output pin

When synthesis reports No path found, it just means this type of path does not exist in your design. And so it can't report any timings.

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  • \$\begingroup\$ Even adding an XST constraint file (*.xcf!) would not change the result. "No path found" is reported because the design does not have any inputs (according to the report snippet). \$\endgroup\$ – Martin Zabel Nov 14 '15 at 21:28
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It is not an error.

Minimum input arrival time before clock: No path found

This simply means that there is no logic path from any input to a flip-flop (or latch).

Maximum combinational path delay: No path found

And this means that there is no logic path from any input to any output without a flip-flop in between (= combinational path).

It seems that your design does not have any inputs.

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Minimum period: 2.334ns (Maximum Frequency: 428.376MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 1.282ns Maximum combinational path delay: No path found

Hi!

Your code is correct and synthesis too. Better You apply input values directly at that statement only instead of applying in testbench. Then you can observe combinational path delay.

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