After synthesis of my verilog code. I am getting the below timing report. I think it showing any mistake in my code.
Speed Grade: -2
Minimum period: 2.334ns (Maximum Frequency: 428.376MHz)
Minimum input arrival time before clock: No path found
Maximum output required time after clock: 1.282ns
Maximum combinational path delay: No path found
The main thing which bother me is the comment highlighted by bold. Is it showing of any kind of error?