I'm working on a PCB for the MP2617. That IC integrates a buck converter and has two physical SW pins sandwiching the VIN pin, as shown in my tentative layout below. No other pins on the IC are doubled. So I'm wondering if the doubled SW pin is to increase the current capacity or just to provide more layout options. I should note that the device will be operating at the top end of its input voltage and step-down ratio capability (14 V to 3.6 V), and 2/3 of its output current rating of 3 A. The estimated inductor peak current is 2.5 A

  • can I safely leave one of them unconnected?
  • should I connect them together by a 10 mil trace inside the IC footprint (replacing the existing ground trace), even though it will come very close to the small signal pins on the right hand side, and the 10 mil trace will have little current capacity?
  • should I connect them together by a trace and two vias on the left of the IC, at the cost of reducing the width of the PGND and VIN traces?

The datasheet is mute on that matter.


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    \$\begingroup\$ I would guess it is one to have it nearer to power ground for actual switching, and the other have nearer to the bootstrap for the bootstrap cap. Btw. are you sure it is a good idea to connect power ground and analogue ground at that place? \$\endgroup\$ – PlasmaHH Jul 28 '15 at 10:18
  • \$\begingroup\$ @PlasmaHH I'm quite sure there are better places to connect them \$\endgroup\$ – Asmyldof Jul 28 '15 at 12:54
  • \$\begingroup\$ As for the ground, I am sure of nothing, as this is my first PCB ;-) But I have seen such a layout with AGND connected to PGND under the IC in AN136, albeit with a larger package that has a thermal pad. What would be the issue with the current ground connection? The AGND occupies the top right quadrant, not mixing with PGND and connects to PGND only under the IC. \$\endgroup\$ – Damien Jul 28 '15 at 13:28
  • \$\begingroup\$ @Damien But your AGND doesn't connect to anything else. Connecting grounds together is best done in a star-configuration, but this looks like analogue components reach the AGND through your PGND domain. That could give annoying oscillations or reduced performance, because switching noise gets "injected" from PGND into your Analogue reference ground in the chip. May not happen, but 2A switching currents... it definitely could. \$\endgroup\$ – Asmyldof Jul 28 '15 at 13:37
  • \$\begingroup\$ AGND leaves the IC footprint through the pin at the top and forms a large pour over the whole top right quadrant of the board, where the small signal circuits are. I should have included that in the screencap. \$\endgroup\$ – Damien Jul 28 '15 at 13:40

you say no other pins are doubled, but I see the PGND under two pins as well, possibly even four.

This is a synchronous buck chip with internal switch, it's very possible the low-impedance path is (, as Plasma says in the comments,) between the three pins closely put together:
where the top SW is more of a looped-around after thought. The power path should definitely include the other pin with least amount of impedance possible (few vias in series or many in parallel and thickest trace as you can get).

It is possible the SW pins are in direct parallel on the chip and they both jump over the bulk VIN with wire bonds of the same or similar description, but in matters of chip design it seems less likely. If they both offer a same or similar path, the only thing I can think of would be one pad being closer to the high-side switch and the other closer to the low-side switch, which would then again mean both need to be connected as low-impedance as you can.

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  • \$\begingroup\$ There is only one PGND, the other pins connected to it are configuration pins that can be driven high or low to set the circuit behaviour. I see what you mean about the top SW pin being an afterthought. Wouldn't they mention it in the datasheet if it had no current capability? \$\endgroup\$ – Damien Jul 28 '15 at 13:30
  • \$\begingroup\$ If I want to connect the inductor to both pins or to the lower pin, then either (a) the path from VIN to CIN has to go through vias or (b) the path from SW to the inductor has to go through vias or (c) the return from CIN to PGDN has to go through a via. None of these seem good. \$\endgroup\$ – Damien Jul 28 '15 at 13:32
  • \$\begingroup\$ @Damien Fair enough. It is not impossible that they equipped the other SW pin with the capability to be used as a main connection, but with power electronics one should always assume that 2 pins in a power path both need to be connected for carrying the load, unless specifically told otherwise in the datasheet. \$\endgroup\$ – Asmyldof Jul 28 '15 at 13:32
  • \$\begingroup\$ Ah, I see another option (d) the second SW trace goes under CIN, between its pads, and joins the inductor without vias. \$\endgroup\$ – Damien Jul 28 '15 at 13:35
  • \$\begingroup\$ @Damien if you can, I think your D is the best, moving the "signal" GND connections away from under the chip, leaving room for a SW trace. Power carrying traces >> signal traces. I have no time to fully scour the PDF, so I cannot make promises about best practise, but if you're sure it tells you nothing, and you are stuck to 2-sided (which you probably are for a first design, no shame in that..) I would give preference to D. \$\endgroup\$ – Asmyldof Jul 28 '15 at 13:39

This is a fairly high frequency (up to 1.6MHz) switcher- you may wish to follow the manufacturer's evaluation board layout on this particular matter. As you can see, the pins are both connected together on a 2-layer layout.

enter image description here

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  • \$\begingroup\$ I didn't know about that demo board — thanks, that will be a great help. \$\endgroup\$ – Damien Jul 28 '15 at 17:58

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