What is equivalent VHDL code of these verilog lines:

dfslckd_q <= #TCQ DFSLCKD;   
dfslckd_rising <=#TCQ !dfslckd_q & DFSLCKD;

Signals are all bit (TCQ has this declaration: parameter TCQ = 1;) and code is in clocked block.


It depends on the time resolution in Verilog, but making the assumption that

parameter TCQ = 1;

means an inertial clock-Q delay of 1 ns, you can translate this declaration into VHDL as

constant TCQ : time := 1 ns;

then your lines become

dfslckd_q      <= DFSLCKD after TCQ;
dfslckd_rising <= (not dfslckd_q) and DFSLCKD after TCQ;
  • \$\begingroup\$ Understood ! .. so #TDQ is the flop delay I suppose Many thanks Brian. \$\endgroup\$ – V-italiano Jul 29 '15 at 11:14
  • \$\begingroup\$ If your signals have pulses shorter than TCQ that you want to pass through, you need to use dfslckd_q <= transport DFSLCKD after TCQ;. Also you should mark Brian's answer as correct! \$\endgroup\$ – scary_jeff Jul 29 '15 at 15:25
  • \$\begingroup\$ @scary_jeff : OK, so Verilog doesn't do inertial delays? Or has a different syntax for them? \$\endgroup\$ – Brian Drummond Jul 29 '15 at 17:41
  • \$\begingroup\$ @BrianDrummond I don't know anything about Verilog, sorry. Just wanted to mentioned that VHDL transport may be required, depending on what his signals are doing. \$\endgroup\$ – scary_jeff Jul 30 '15 at 11:23

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