Crossing a single-cycle spike signal from a fast clock domain to a slower one

Question

I have a 1-bit signal coming from a part of my circuit that is running on a 40 MHz clock. The signal is mostly 0, except it is 1 for a single 40 MHz-cycle every ~million cycles.

Another part of my circuit is running on a 1 MHz clock. I would like to do some synchronous processing on the signal described above in this part of my circuit. What is the correct way to turn the single-cycle 40 MHz signal into a single-cycle 1 MHz signal?

In case that matters, both the 40 MHz and the 1 MHz clocks are output from the same clock manager driven by the 32 MHz clock on my dev board, so they should be phase-locked.

Answer 1

Convert that pulse to a level change (invert the output of a flip flop whenever a pulse is generated), pass that across with a couple of flip flops for synchronization, and convert the level change back to a pulse with a flip flop and XOR gate. This is called pulse synchronization with a toggle synchronizer, and it is a very common technique. See: http://www.edn.com/electronics-blogs/day-in-the-life-of-a-chip-designer/4435339/Synchronizer-techniques-for-multi-clock-domain-SoCs .

Answer 2

Edit: This solution assumes you don't have access to the 40 MHz clock. If you do, then the answer by @alex.forencich is better.

Why don't you use the 40 MHz pulse as an asynchronous set for a register in the 1 MHz domain. If you then have a double-register synchroniser after this, followed by a rising edge detector, you can use the 1 MHz pulse output by the rising edge detector to trigger whatever other logic you have, and act as a synchronous clear on the first register (the one with an async set).

signal async_reg : std_logic := '0';
signal synchroniser : std_logic_vector (2 downto 0) := (others => '0');
signal rising_edge_detected : std_logic;

...

process (clk1MHz)
begin
  if (pulse40MHz = '1') then
    async_reg <= '1';
  elsif (rising_edge(clk1MHz)) then
    if (rising_edge_detected = '1') then
      async_reg <= '0';
    end if;
  end if;
end process;

process (clk1MHz)
begin
  if (rising_edge(clk1MHz)) then
    synchroniser <= synchroniser(1 downto 0) & async_reg;
  end if;
end process;

rising_edge_detected <= synchroniser(1) and not synchroniser(2);