How does PWM frequency affect the AND gate performance? And, is this a limitation of this chip or technology?
Using a PWM signal set to 20 KHz on the input, along with +5V on the AND gate the output was zero volts when the PWM was set to less than 50% on. However, the results were much improved when frequency was reduced to 5 KHz--and 5 KHz is an acceptable max frequency, but still having problems at the low end.
I sent this part out, so we are using a multimeter, rather than a scope, to measure. For 5 KHz frequency the PWM in and out are different--of course the absolute voltage values will be different, but the trend or slope should be the same. In other words, if graphed, the voltage reduction from 100% to 0 should be roughly the same for the input and output PWMs. We do not see this at 10%, rather it drops to zero.
Power %,Pin 1 vdc, Pin 3 vdc
10 .29 0
20 .68 .34
30 1.20 .72
40 1.75 1.62
50 2.34 2.42
60 2.96 3.15
70 3.60 4.10
80 4.18 4.78
90 4.65 5.42
100 4.99 5.44
So, as you can see, it is pretty much the same as in the white box. At low power (below 20%), I basically get nothing at pin 3.
The pinouts on the breadboard are: pin 1 is PWM Pin 2 is +5V DC
pin 7 is 5V DC ground and PWM ground pin 14 is +5V dc
In an effort to debug my problem, I removed this chip from its socket and put it on a breadboard. However, I got the exact same results on the breadboard. To keep this question simple, it will be stated using the breadboard (not shown).