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How does PWM frequency affect the AND gate performance? And, is this a limitation of this chip or technology?

Using a PWM signal set to 20 KHz on the input, along with +5V on the AND gate the output was zero volts when the PWM was set to less than 50% on. However, the results were much improved when frequency was reduced to 5 KHz--and 5 KHz is an acceptable max frequency, but still having problems at the low end.

I sent this part out, so we are using a multimeter, rather than a scope, to measure. For 5 KHz frequency the PWM in and out are different--of course the absolute voltage values will be different, but the trend or slope should be the same. In other words, if graphed, the voltage reduction from 100% to 0 should be roughly the same for the input and output PWMs. We do not see this at 10%, rather it drops to zero.

Power %,Pin 1 vdc, Pin 3 vdc

10 .29 0

20 .68 .34

30 1.20 .72

40 1.75 1.62

50 2.34 2.42

60 2.96 3.15

70 3.60 4.10

80 4.18 4.78

90 4.65 5.42

100 4.99 5.44

So, as you can see, it is pretty much the same as in the white box. At low power (below 20%), I basically get nothing at pin 3.

The pinouts on the breadboard are: pin 1 is PWM Pin 2 is +5V DC

pin 7 is 5V DC ground and PWM ground pin 14 is +5V dc

In an effort to debug my problem, I removed this chip from its socket and put it on a breadboard. However, I got the exact same results on the breadboard. To keep this question simple, it will be stated using the breadboard (not shown).

74HC08 AND gate

Whole circuit board ICs on circuit board that I made

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  • \$\begingroup\$ Where did you source the chip from? Also, what is generating the PWM? \$\endgroup\$ – Ignacio Vazquez-Abrams Jul 30 '15 at 3:34
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    \$\begingroup\$ At 20kHz you're a very long way away from the limitations of a 74HC08. \$\endgroup\$ – Brian Drummond Jul 30 '15 at 10:07
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First, you need to tie unused inputs (2A, 2B, 3A, 3B, 4A, 4B) to ground. Leave unused outputs floating. HCMOS inputs tend to float to a mid-level "metastable" voltage which causes much higher power consumption in the chip because the input transistors are staying in their active region.

Second, you're just using the AND gate as a buffer, while you have a perfectly good 74HC04 (which probably has a better output driver) right there. Why?

Third, PWM is a digital signal. It alternates between 0 and 5 V in this case. You need a scope to see what it's doing; a multimeter is right out. What you're doing is you're expecting the meter to somehow average the PWM signal for you. Any nonlinearities and bandwidth limits the meter has will get you false results.

If you want to convert PWM to an analog voltage, you have to pass it through a low-pass filter of some form, where the corner frequency of the filter is set higher (preferably much higher) than the highest analog frequency you want to output, and lower (hopefully much lower) than the PWM switching frequency. 5 kHz and 20 kHz are probably too close.

For a 5 kHz max analog signal, your filter should have a corner frequency of 10 kHz or more, and the PWM should be at least 8X the max frequency (40 kHz).

For filter design, please see TI's WEBBENCH or FilterPro.

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Just add this low-pass filter after the gate, and compare the readings you get:

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ I purchased these parts and tested. The result was that the output signal because a single voltage (no longer a PWM signal). When the input signal was varied, the output voltage would increase and decrease. In other words, on the scope I saw the horizontal line move up and down. \$\endgroup\$ – Allen Aug 4 '15 at 8:20
  • \$\begingroup\$ That is the expected result. Measure the output voltage of the circuit with a digital voltmeter to get an accurate measurement of the average PWM voltage at the AND gate output. \$\endgroup\$ – Spehro Pefhany Aug 4 '15 at 11:41

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