In the Art of Electronics there is an assertion that if a bias is established with 0.5 the supply voltage, the transistor will saturate if the temperate goes up 8ºC. The schematic is the basic one for common emitter.

I tried to verify that the collector-emitter voltage became zero or less. However I can't manage to get it right. If we start by taking the V_BE voltage as 0.6, it would go down to .5832, but how can we use that to verify it saturates?


  • \$\begingroup\$ OFRBG, I am not sure if you correctly understand the temperature effect. It is not the case that "VBE would go down". The background of the "magic" value of -2mV/K is the following: For VBE=const. the collector current Ic will go up for rising temperatures - and it can be brought back to the initial value if the voltage VBE would be reduced (externally) by -2mV per one deg. temp increase. \$\endgroup\$ – LvW Jul 31 '15 at 7:28
  • \$\begingroup\$ LvW, thanks. I didn't know the effect worked that way. I appreciate the clarification! \$\endgroup\$ – Cehhΐro Jul 31 '15 at 15:20

You know that \$\text I_c\$ = \$\text I_s e^{V_{BE}/Vt}\$

To get the transistor to saturate you have to double the collector current, so if you consider \$\frac{\text I_{c1}}{\text I_{c2}} = 2\$, then

\$\Delta V_{BE}\$ = ln(2)Vt = 18mV, assuming Vt = 26mV (room temperature)

So a base voltage delta of 18mV will cause the collector current to double. If we assume the base voltage divider is 'stiff', then a \$\Delta V_{BE}\$ from 0.600 to 0.582 will cause the transistor to saturate.

  • \$\begingroup\$ I see, I see. So you need in this case to have a delta of 18mV. If we have that delta then the current doubles. But changing 8 degrees in temperature has a 16.8mV delta. Did I miss something? \$\endgroup\$ – Cehhΐro Jul 30 '15 at 22:23
  • \$\begingroup\$ Also, may I ask another question? That first equation refers to base-emitter voltage, so under this model how do we control the collector current if base-emitter voltage depends only on temperature? \$\endgroup\$ – Cehhΐro Jul 30 '15 at 22:43
  • \$\begingroup\$ No, I think it's just an approximation. If you use 25mV for Vt you get 17mV. \$\endgroup\$ – Spehro Pefhany Jul 30 '15 at 22:43
  • \$\begingroup\$ It depends on Is which is a transistor characteristic. The point is that you can only badly control the collector current. You'd have to trim the divider to get it biased in the middle, then as soon as the temperature changes a bit (or you use a different transistor or the supply voltage changes) the transistor saturates or the collector voltage increases toward the plus rail. So don't do it, is their point. \$\endgroup\$ – Spehro Pefhany Jul 30 '15 at 22:51
  • \$\begingroup\$ So with the Ebers-Moll model we need to consider this exponential. Then how would a larger emitter resistor stabilize the biasing, under this same model? (Sorry about the trouble.) \$\endgroup\$ – Cehhΐro Jul 30 '15 at 23:13

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