# Why is CMOS fall time faster than rise time?

I've just started a computer architecture class, and the slides from a lecture says that the reason why fall time is faster than rise time is that the NMOS electrons have more mobility than PMOS which has holes. Does anyone know how to explain this in simple terms?

The answer lies in Carrier Mobility of Silicon. A CMOS stage has a P channel device from Vdd and an N channel device to Vss. Note the much higher mobility of electrons vs. holes.

The rise time at the output depends primarily on how fast the P channel device can turn on, and the fall time is determined primarily by how fast the N channel device can turn on.

The majority carrier in P channel devices is holes, and the majority carrier in N channel devices is electrons.

As electrons are in the conduction band and holes are in the valence band (same link), N channel devices are inherently faster in switching than P channel devices given equal physical parameters.

In many newer logic families, the length - width ratios of the transistors are adjusted to give symmetric switching times.

• I think it is no correct to say "The rise time at the output depends primarily on how fast the P channel device can turn on, and the fall time is determined primarily by how fast the N channel device can turn on." What matters actually is the time it takes to change the voltage of the output. Even if both transistors can turn on in the same time, "on" for the N-MOS transistor may mean 5 Ohm and "on" for the P-MOS transistor may mean 8 Ohm between Source and Drain resulting in different fall and rise times. – Curd Jul 31 '15 at 14:13
• Also your last sentence supports my objection. Carrier mobility (or turn-on time) is not affected by length or width of the transisor. Length and width, however, affect the on-resistance. – Curd Jul 31 '15 at 14:19

For some reason it is easier to get $R_{on}$ small for N-MOS than for P-MOS transistors.

The N-MOS transistor is in charge of setting the ouput low, i.e. discharging the line capacitance and gate capacitances of the connected inputs which is faster when $R_{on}$ is smaller.