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I am developing a pipeline.

This pipeline has parallel flows of execution.

What i need to know is, how to branch the pipeline and later how to fold it back ?

(this question has nothing to do with the instruction branch and return).

Prev. Unit -> Stage0 ----> Stage1 -+-> Stage2 -> Stage3 -> Stage7 -> Next unit
                              ^    |                              
                              |    +-> Stage4 -> Stage5 -> Stage6 -+
                              |                                    |
                              +------------------------------------+

This is what i want to know, how to branch (Ie. have more than one possible next stage) and then fold back (have a unit that might take data from two different stages).

If data+opcode goes thru Stage4, Stage5 and Stage6 Stage0 must stop sending data (this part of the pipeline should stall) because Stage4 means a cache miss (stage1 is the CAM memory that will tell if the page is on the cache or not), if the data is on the cache, stage2 takes it and Stage3 operates on it. Else, Stage4, Stage5, Stage6 (arbitrary size) will evict one page and load the correct page into the unit cache.

So i need to be able to "branch" the pipeline based on if the page is on the cache or not. But, if the page is not on the cache, proabably everything else will cachemiss too, so i need to stall the pipeline (but not everything else i would not be able to handle the cache miss).

The problem is my pipeline stages are made out of D flip-flops that forward a word each clock cycle. If i dont prevent the clock from cycling, data will simply drop.

Is there a standard way to implement flow control for branches in the pipeline ?

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    \$\begingroup\$ @Junior I Strongly disagree. Pipeline design is a part of digital design. That being said, it isn't clear enough to answer in its current state. \$\endgroup\$
    – W5VO
    Jul 31, 2015 at 11:58
  • \$\begingroup\$ Is your question about how to hold a D flip-flop's state even when it is clocked? You could either gate the clock (so that it is not actually clocked), or gate the data on all of them so that D is equal to Q in "stall mode". \$\endgroup\$
    – Justin
    Jul 31, 2015 at 13:25
  • \$\begingroup\$ hm... it would be better something like CTS x RTS, ie, a flow control that could signal all the way back to the source that the pipeline jammed somewhere, they i simply signal CTS = LOW on stage 1 meaning "i cant take more data" and work from it. Stage1 will then watch for his second input for data comming from the cache miss handling (=reload the address that you wanted to access because now it is on the cache). \$\endgroup\$
    – Jorge Aldo
    Jul 31, 2015 at 14:13

1 Answer 1

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Found a solution.

My pipeline is made out of D-type latches that forward opcode + data (if any) each clock cycle. Each stage is made out of combinational logic (ex. ALU) plus a d-latch that feeds the stage.

To stall the pipeline (or selected parts of it) I must OR the clock source with the Q output of a R S flip-flop. If the cache unit needs to stall the pipeline (the whole of it) it can simply set the flip-flop, float the latches that drive the CAM memory and the Cache RAM address input/output and then manipulate the cache, then reset the flip flop, leting the pipeline flow again.

As the clock is ORed with a flag, the D-type flip-flops will store the last value they see and foward it as soon as the clock raises again. Latches must not be clocked by the clock edge or this will fail.

The cache handling (as the whole processor needs to stop if a cache miss or TLB miss happens) and MMU is done in a single unit that watches the pipeline for a miss, stalls everything and handles the issue.

Anybody see a problem with that solution ?

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