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If I understand it correctly, you use a PLL in an FPGA to get a higher clock from, say, a 50 MHz oscillator by synchronizing the faster clock to the slower reference one. Like if I had a 50MHz crystal and wanted to run my FPGA at 200 MHz, I'd use the PLL to lock the phase so every 4th pulse of the board clock matches the rising edge with the 50 MHz reference rising edge. So it sounds like the PLL here is correcting for error in the multiplied clock signal.

My question is, if I wanted to try this with MY FPGA, and make one of these PLL multipliers myself, where does the new faster clock come from? My first guess would be just using a bunch of buffers and an inverter and letting the propogation delay act as the timing in between pulses, but I'm not sure if this is the correct way to do this.

Also, how would I figure out the practical limits for how fast a clock I can run? Do I just run a simulation of my end circuit, look at the delay it takes for the outputs to stabilize, and use that as my maximum clock speed, or are there other considerations I need to make?

Thanks for any help you can give.

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  • \$\begingroup\$ PLLs are Analogue, you can't make one yourself in an FPGA, only instantiate ones that may already be present. There are tricks you can do with delay chains to double the frequency, but they will be highly jittery and temperature dependent. \$\endgroup\$
    – Tom Carpenter
    Commented Jul 31, 2015 at 12:59
  • \$\begingroup\$ The oscillator you describe (buffers + 1 inverter) is called a ring oscillator. It is a free-running oscillator though, so you can't use it as the VCO (voltage controlled oscillator) in a PLL. \$\endgroup\$
    – Justin
    Commented Jul 31, 2015 at 13:05
  • \$\begingroup\$ @Justin, I'm no expert, but I believe it is possible to tune a ring oscillator by either power starving the gates. \$\endgroup\$
    – The Photon
    Commented Jul 31, 2015 at 16:45
  • \$\begingroup\$ Yes, you can also tune one using varactors, but if those are available (or if you can power-starve the gates), I don't think it's just using standard FPGA logic cells anymore. An FPGA could certainly include such a tunable VCO on the die, though (perhaps some do?). \$\endgroup\$
    – Justin
    Commented Jul 31, 2015 at 18:45

2 Answers 2

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For a PLL Clock multiplier, where does the new clock come from?

Usually it comes from a voltage controlled oscillator (VCO) - it runs at the higher speed and then there is a digital divider that reduces this frequency to what would be nominally (say) 50MHz to match your reference crystal frequency. The PLL has a frequency/phase (PFD) detector that outputs a dc level when the two frequencies are not in-lock. This dc level drives the VCO and nudges it to alignment so it is exactly producing a mulitple of 50MHz.

enter image description here

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A PLL is a normal voltage controlled oscillator (VCO).

This VCO first generates a wave that is roughly the right frequency, and then the feedback mechanism is used to tune it. For tuning, the phase of two (slower) clocks, generated by dividing the input and the output clock, respectively, is compared.

Multiplication works by dividing the output clock before comparison.

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