If I understand it correctly, you use a PLL in an FPGA to get a higher clock from, say, a 50 MHz oscillator by synchronizing the faster clock to the slower reference one. Like if I had a 50MHz crystal and wanted to run my FPGA at 200 MHz, I'd use the PLL to lock the phase so every 4th pulse of the board clock matches the rising edge with the 50 MHz reference rising edge. So it sounds like the PLL here is correcting for error in the multiplied clock signal.
My question is, if I wanted to try this with MY FPGA, and make one of these PLL multipliers myself, where does the new faster clock come from? My first guess would be just using a bunch of buffers and an inverter and letting the propogation delay act as the timing in between pulses, but I'm not sure if this is the correct way to do this.
Also, how would I figure out the practical limits for how fast a clock I can run? Do I just run a simulation of my end circuit, look at the delay it takes for the outputs to stabilize, and use that as my maximum clock speed, or are there other considerations I need to make?
Thanks for any help you can give.