For my senior high school project I decided to build a basic CPU from discrete components. I plan on using a 5V logic level and the current design calls for around 2000-3000 N-channel MOSFET transistors. This question is specifically about the value of the pullout resistor in NMOS logic.

In my breadboard testing I just used 10k resistors as I had a bunch lying around and the value is typical for a pull-up resistor so it seamed reasonable, but it may not be optimal for what I'm trying to accomplish.

As far as I understand the choice of this value is a tradeoff between the power consumption of the CPU and the speed it takes each gate to reach its output value and therefore the max clock speed I could drive it at.

Power consumption: Lets assume that each transistor has one 10k resistor and all transistors are on. As typical values for R_dson are much less then 10k we can ignore them. This means the power consumption would be on the order of 3000*(5^2)/10000=7.5 watts. This seams surprisingly low - is this value reasonable?

Clock speed: Here I'm more in the dark. At what clock speed would I be able to drive NMOS circuitry with a 10k pull up vs. a 1k pull up? How would that compare to CMOS circuitry using comparable MOSFET?

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    \$\begingroup\$ 7.5W sounds reasonable to me. 1.5A at 5V, that power level wouldn't go well in a DIP package, but in discrete parts spread over several square feet of circuit board it would not cause a problem. \$\endgroup\$ – Jasen Aug 2 '15 at 6:36
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    \$\begingroup\$ I hope you're designing this in a modular way. A 2000-transistor logic circuit sounds like a nightmare to debug... \$\endgroup\$ – Adam Haun Aug 2 '15 at 13:15
  • \$\begingroup\$ I planed on building each "large scale" (eg register, adder, inc) on a separate board and Debug each one separately (testing each design on a beardboard first) \$\endgroup\$ – Michal Aug 2 '15 at 20:33
  • \$\begingroup\$ I think an interesting approach for implementation would be to build a small circuit board that contains three 3-input NOR gates, and use this as your basic building block. It would have 14 connections along one edge, allowing it to be plugged into a breadboard for design, or into a wirewrap board (for example) for a more permanent setup. You could do a custom PCB, or build it on a Uni-SIP board. Two such modules would be used to make an edge-triggered D flip-flop. The original Cray-1 was built in a similar manner, except they used an actual IC. \$\endgroup\$ – Dave Tweed Aug 2 '15 at 21:10
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    \$\begingroup\$ ... Your board could include a small LED on the output of each gate, which would help with debugging ... and also look really cool when the machine is fully assembled and running! \$\endgroup\$ – Dave Tweed Aug 2 '15 at 21:10

The timing would depend primarily on the capacitive load on each logic gate, which would include both the wiring capacitance and the capacitance of the MOSFET gate(s) you're driving.

For example, the 2N7000 has an input capacitance of 20 pF typical (50 pF max). If your average fanout is 3, plus some wiring capacitance, that gives you a typical load of 100 - 200 pF. With a 10K pullup, that gives you an R-C time constant of 1 - 2 µs. You'd probably need to allow at least two time constants for one "gate delay" for reliable switching, so we're talking about 2 - 4 µs per gate.

To get useful work done, you'll need to allow some maximum number of gate delays per clock period. This will depend on your specific design, but a number like 6 to 10 would be typical. So now we're talking about a clock period of 12 - 40 µs, or frequencies in the range of 25 - 80 kHz.

Switching to a 1K resistor would allow the frequency to scale up by roughly a factor of 10.

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    \$\begingroup\$ These numbers make me appreciate modern processor cores even more, with their switching speeds around microwave ovens that actually result in calculations is pretty close to magic. \$\endgroup\$ – KalleMP Aug 2 '15 at 15:35
  • \$\begingroup\$ In the case of CMOS logic would using R_DSon of the MOSFET as the resistance for the RC circuit yield reasonable results? \$\endgroup\$ – Michal Aug 2 '15 at 19:32
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    \$\begingroup\$ Yes, that's one of the benefits of CMOS. The other is being able to shut off the pullup altogether when the output is low, eliminating the static power dissipation. \$\endgroup\$ – Dave Tweed Aug 2 '15 at 20:51

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