For my senior high school project I decided to build a basic CPU from discrete components. I plan on using a 5V logic level and the current design calls for around 2000-3000 N-channel MOSFET transistors. This question is specifically about the value of the pullout resistor in NMOS logic.
In my breadboard testing I just used 10k resistors as I had a bunch lying around and the value is typical for a pull-up resistor so it seamed reasonable, but it may not be optimal for what I'm trying to accomplish.
As far as I understand the choice of this value is a tradeoff between the power consumption of the CPU and the speed it takes each gate to reach its output value and therefore the max clock speed I could drive it at.
Power consumption: Lets assume that each transistor has one 10k resistor and all transistors are on. As typical values for R_dson are much less then 10k we can ignore them. This means the power consumption would be on the order of 3000*(5^2)/10000=7.5 watts. This seams surprisingly low - is this value reasonable?
Clock speed: Here I'm more in the dark. At what clock speed would I be able to drive NMOS circuitry with a 10k pull up vs. a 1k pull up? How would that compare to CMOS circuitry using comparable MOSFET?