Interim update

Okay, I just realized I screwed up on the simulation. When I added \$C_{bp}\$ I upset the "break" in the feedback loop necessary to get the loop gain. The left-side lead has to go to the FB node leaving the INV node the only thing connected to the inverting input. I just fixed it and now the plot looks like one would expect (and my phase margin is all gone :). I'll work it through and then may take the question down since I'm not sure it happens when one doesn't screw up like I did :)

I'm finally getting a handle on methodical frequency response compensation for op amp circuits. I got LTspice set up to show loop gain, and have compensated this circuit in a fairly conventional way. I'm not sure what the name of this compensation strategy is, if it has one, but as I understand it, after "isolating" the gate capacitance with \$R_{iso}\$ it adds a zero to the feedback circuit at the frequency determined by \$\frac{1}{2\pi C_{bp} R_f}\$, about 1MHz in this case.

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The feedback circuit frequency response looks like this:

enter image description here

The phase margin is a healthy 64 degrees, which I'm happy about because I'd prefer this circuit to be overly stable rather than get every last bit of speed out of it.

My question is: Should I be concerned that the gain rises back above 0dB at about 1.5MHz?

Also I'm a little bit concerned that the phase drops so precipitously in that neighborhood, wondering if I should be looking to add another pole somewhere or perhaps relocate one I already have.

  • \$\begingroup\$ What kind of model are you using to model the LM358? IIRC the unity gain frequency for the LM358 is around 1MHz, and it is internally unity-gain compensated, therefore a bit above that frequency there should be the first higher order pole of the opamp. Maybe the model you are using doesn't take this into account. Try to use LTSpice UniversalOpamp2 setting the spice model as model.3a or model.3b. More details in the example/educational/UniversalOpamp2.asc file inside LTspice directory. \$\endgroup\$ – Lorenzo Donati -- Codidact.com Aug 3 '15 at 1:42
  • \$\begingroup\$ I'm using the TI (National Semi) model located here: ti.com/lit/zip/snom247 . It definitely includes the pole at 2MHz (an earlier/older one I tried didn't). Do I take it you believe the jump back up above 0dB is an artifact of the simulation and wouldn't be observed on the bench? \$\endgroup\$ – scanny Aug 3 '15 at 2:37
  • \$\begingroup\$ Yes, that was my concern. But since the model has two poles it shouldn't be that the cause. Anyway I would give the UniversalOpamp2 a try, just to have another data point. \$\endgroup\$ – Lorenzo Donati -- Codidact.com Aug 3 '15 at 2:53

The rise of the gain above app. 1.5 MHz is caused by the capacitor Cbp, of course. As can be seen, a part of the test signal is coupled to the opamp output directly via Cbp: For rising frequencies the opamp output voltage continuously decreases and the output impedance increases so that the effect of the signal through Cbp also increases with frequency. (The same effect can be observed for Sallen-Key lowpass filters).

By the way - what is the purpose of Cbp? "Upset" the break of the feedback loop? This is not necessary for simulating the loop gain response. Note that this capacitor deteriorates the loop gain function.

  • \$\begingroup\$ Linear Tech has a video here: linear.com/solutions/4449 that explains how to plot loop gain using LTspice. They call it open-loop gain, which of course is something quite distinct, but nevertheless the procedure is quick and appears to work nicely. That's what the FB and INV nodes are about and the 0VDC AC 1 voltage source in this schematic. I just hooked up the "bypass" cap to INV when I should have connected it to FB. When I fixed that I got a normal-looking Gain/Phase plot and the weird gain reversal was gone. Of course now I have to choose all new component values :) \$\endgroup\$ – scanny Aug 4 '15 at 2:54

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