Short: The hysteresis specification ensures that the negative going transition voltage is always greater than the positive going transition voltage.
Define:
- Vtpos = input transition voltage with Vin increasing
- Vtneg = input transition voltage with Vin decreasing
- Vhyst = Vtpos - Vtneg for a given IC and conditions.
Look at delta-Vt figure in table 7.7. 3rd line on page 5 in datasheet.
This guarantees:
a minimum hysteresis of 0.4V and
a maximum of 1.4V at Vcc=4.5V and 25 degrees C.
Vhyst = 0.4 to 1.4 V
This spec is then read in conjunction with values for Vt positive and negative going.
Vt pos going = 0.9 to 1.9
Vt neg going = 0.5 to 1.5
Without the hysteresis spec this suggests that the negative going level MAY be above the positive going level (which makes no sense) BUT add the hysteresis spec as well and it makes sense.
With Vt neg = 0.5V then Vtpos MUST be >= (Vtneg + hyst min) = 0.5 + 0.4 = 0.9V.
and can be as high as 0.5 + 1.4 = 1.9V.
The following may bend the brain somewhat - it's not strictly necessary to follow it if you just follow the above ranges. [E&OE - if I've accidentally said something wrong plase point it out - easily done in such cases].
ie it is seen that with Vtneg at it's minimum values the addition of the range of possible hysteresis value gives exactly the range of Vtpos values - which is as it should be.
However, Vtneg max + hysteresis range = 1.5 + (0.4 to 1.4) = 1.9 to 2.9 which is from the max level of vtpos or above - ie if the negative value is at a maximum of 1.5V then Vtpos will be at its max value of 1.9V. ie when Vtneg is at it's maqximum value the hysteresis range will be at it's minimum. If this was not so then rather high values of Vtpos could result.
It is easy enough to draw a 'state diagram' from the above showing areas of valid operation. There can never be any overlap. ie for a given situation Vtpos will always be > Vtneg.
