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I'm designing an ALU in VHDL. In another file called adder16bit I've designed my adder and I want to use it in different ways e.g if the ALU_OP is ADD, I want it to do addition, if it is SUB, I want it to subtract etc. I'm using a case statement to detect how to use the adder in the proper way. Apparently port mapping with different inputs in each case statement doesn't work and now I'm stuck.

The errors that I'm getting:

Error (10500): VHDL syntax error at ALU.vhd(26) near text "port"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at ALU.vhd(35) near text ";"; expecting ":=", or "<="
Error (10500): VHDL syntax error at ALU.vhd(38) near text "port"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at ALU.vhd(47) near text ";"; expecting ":=", or "<="
Error (10500): VHDL syntax error at ALU.vhd(50) near text "port"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at ALU.vhd(59) near text ";"; expecting ":=", or "<="
Error (10500): VHDL syntax error at ALU.vhd(62) near text "port"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at ALU.vhd(63) near text ";"; expecting ")", or ","
Error (10500): VHDL syntax error at ALU.vhd(65) near text "=>"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at ALU.vhd(66) near text "=>"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at ALU.vhd(102) near text "port"; expecting "(", or "'", or "."
Error (10500): VHDL syntax error at ALU.vhd(103) near text ";"; expecting ")", or ","
Error (10500): VHDL syntax error at ALU.vhd(111) near text ";"; expecting ":=", or "<="

code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ALU is
    port(
        ALU_A, ALU_B : in STD_LOGIC_VECTOR(15 downto 0); 
        ALU_output : out STD_LOGIC_VECTOR(15 downto 0);
        ALU_OP : in STD_LOGIC_VECTOR(4 downto 0)
    );
end ALU;
architecture behavioral of ALU is
    signal Nflag, Zflag, Cflag, Vflag : STD_LOGIC;
    signal flagsRegister : STD_LOGIC_VECTOR(15 downto 0);
component adder16bit
    port(
        adder_input_A, adder_input_B : in STD_LOGIC_VECTOR(15 downto 0);
        adder_output : out STD_LOGIC_VECTOR(15 downto 0);
        carry_in : in STD_LOGIC;
        N, Z, C, V : out STD_LOGIC
    );
end component;
begin
    process(ALU_OP)
    begin
        case ALU_OP is
            when "00000" => --problems!
                normalAddition: adder16bit port map(
                    ALU_A => adder_input_A,
                    ALU_B => adder_input_B,
                    ALU_output => adder_output,
                    '0' => carry_in,
                    Nflag => N,
                    Zflag => Z,
                    Cflag => C,
                    Vflag => V
                );
                flagsRegister <= "000000000000" & N & Z & C & V;
            when "00001" =>
                normalSubtraction: adder16bit port map(
                    ALU_A => adder_input_A,
                    not(ALU_B) => adder_input_B,
                    ALU_output => adder_output,
                    '1' => carry_in,
                    Nflag => N,
                    Zflag => Z,
                    Cflag => C,
                    Vflag => V
                );
                flagsRegister <= "000000000000" & N & Z & C & V;
            when "00010" =>
                addWithCarry: adder16bit port map(
                    ALU_A => adder_input_A,
                    ALU_B => adder_input_B,
                    ALU_output => adder_output,
                    flagsRegister(1) => carry_in,
                    Nflag => N,
                    Zflag => Z,
                    Cflag => C,
                    Vflag => V
                );
                flagsRegister <= "000000000000" & N & Z & C & V;
            when "00011" =>
                subtractWithCarry: adder16bit port map(
                    ALU_A => adder_input_A;
                    not(ALU_B) => adder_input_B;
                    ALU_output => adder_output;
                    flagsRegister(1) => carry_in,
                    Nflag => N,
                    Zflag => Z,
                    Cflag => C,
                    Vflag => V
                );
                flagsRegister <= "000000000000" & N & Z & C & V;
            when "00100" =>
                ALU_output <= STD_LOGIC_VECTOR(unsigned(ALU_A) + 1);
            when "00101" =>
                ALU_output <= STD_LOGIC_VECTOR(unsigned(ALU_A) - 1);
            when "00110" =>
                ALU_output <= ALU_A and ALU_B;
            when "00111" =>
                ALU_output <= ALU_A or ALU_B;
            when "01000" =>
                ALU_output <= ALU_A xor ALU_B;
            when "01001" =>
                ALU_output <= SHIFT_LEFT(unsigned(ALU_A), ALU_B(3 downto 0));
                flagsRegister <= "000000000000" & flagsRegister(3) & flagsRegister(2) & ALU_A(15) & flagsRegister(0); --bit 15 gets shifted into C flag
            when "01010" =>
                ALU_output <= SHIFT_RIGHT(unsigned(ALU_A), ALU_B(3 downto 0));
                flagsRegister <= "000000000000" & flagsRegister(3) & flagsRegister(2) & ALU_A(0) & flagsRegister(0); --bit 0 gets shifted into C flag
            when "01011" =>
                flagsRegister <= "000000000000" & flagsRegister(3) & flagsRegister(2) & '1' & flagsRegister(0);
            when "01100" =>
                flagsRegister <= "000000000000" & flagsRegister(3) & flagsRegister(2) & '0' & flagsRegister(0);
            when "01101" =>
                --set interrupt
                null;
            when "01110" =>
                --clear interrupt
                null;
            when "01111" =>
                ALU_out <= ALU_A;
            when "10000" =>
                LWandSW: adder16bit port map(
                    ALU_A => adder_input_A;
                    ALU_B => adder_input_B;
                    ALU_output => adder_output;
                    '0' => carry_in;
                    Nflags => N,
                    Zflags => Z,
                    Cflags => C,
                    Vflags => V
                    );
            when others =>
                null;
        end case;
    end process;
end behavioral;
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You can't instantiate an entity inside a process.

Use your case statement to select what signals are fed into one instance of the adder16bit entity.

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  • \$\begingroup\$ Alternatively, make adder16bit a procedure instead of a component, converting its port list to a parameter list... \$\endgroup\$ – user_1818839 Aug 3 '15 at 13:57
  • \$\begingroup\$ @BrianDrummond would that introduce the potential for a toolchain to generate repeated logic, once for each procedure call? \$\endgroup\$ – scary_jeff Aug 3 '15 at 15:00
  • \$\begingroup\$ Potentially, yes, good point. It could be a good test for the synth tool's optimisation... \$\endgroup\$ – user_1818839 Aug 3 '15 at 18:40

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