I was running PCI Express reference design simulation in Modelsim. Compilation failed and an error "cannot open top_core.vo file in read mode" was displayed. I went through respective folder, but that particular file was missing. A verilog file with same name (top_core.v) is there is same location.
After going through all the document what I understood is, verilog output file is created by Quartus II when compiled. Then why it is not happening in my case. Is there any other method to make top_core.vo from top_core.v file ?