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I am trying to compute the Fast Fourier Transform (FFT) of 16 parallel input data and therefore, I would like to retrieve 16 output data in parallel. The transform size of my project is N=16.

More specifically, if I understood correctly the datasheet, the current Xilinx FFT IP Core allows to load data one-by-one and therefore, they have to come in sequentially. Moreover, after the FFT operation is completed, data come out also sequentially.

Does anyone have any idea about how to solve my problem ?

I thank you in advance.

Edit:

For posteriority, the full code is available here; details and explanations can be found in the paper.

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  • \$\begingroup\$ Usually, you run the IP core at a greater than or equal speed of data, so serial is quite fine. For instance, if my input comes from an ADC at 100MHz, it's perfectly fine to have a FFT than can input/output 1 sample at a rate of 100MHz. What is your data rate? Do you really receive 16 samples at the exact same time? \$\endgroup\$ Commented Aug 6, 2015 at 15:45
  • \$\begingroup\$ I thank you very much for your interest. I am actually realizing an academic project aiming to improve a system by maximizing its input data rate and I can easily choose the format of my input data. I am working on a Virtex 7 platform and the target clock frequency is around 300MHz without parallelisation (but I still desire to keep the higest possible clock frequency after parallelization). I heard it might be possible to parallelize the output (while keeping a serialized input) and it seems to be an acceptable solution. Do you have any idea about how to realize that ? \$\endgroup\$
    – asonnino
    Commented Aug 7, 2015 at 12:53
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    \$\begingroup\$ Easiest way is to perform convolution, it would cost you 16 complex multiplier-accumulator. This is the solution that cost the less logic, but the most DSP blocks. You can cut that in half by using a pre-adder and adding some control logic. \$\endgroup\$ Commented Aug 7, 2015 at 13:25
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    \$\begingroup\$ Thank you for suggesting that path! Can you explain me a bit more where exactly do you intend to put the convolution block ? I still don't understand how can the convolution give me a parallel FFT output \$\endgroup\$
    – asonnino
    Commented Aug 7, 2015 at 17:38
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    \$\begingroup\$ Definition of Discrete Fourier Transform on 16 points: X_k = Sum_n=0^15 x_n X e^(j*2kn*pi/16). It follows the definition of discrete convolution: h(n) = Sum_m=-inf^inf f(n) g(n-m) when g(n) has closed support (as in DFT). If you prefer, it's a simple multiply-accumulate of the 16 inputs values with the Fourier coefficient. For each X_k, there is 16 multiplication of x_n with e^... and 15 additions of these products. \$\endgroup\$ Commented Aug 7, 2015 at 17:48

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I think you could have been answered more directly. There are many ways to accelerate FFT rate by using parallel structures. A lucid and brief article is found at

http://www.synopsys.com/Company/Publications/SynopsysInsight/Pages/Art1-fpga-signal-processing-IssQ1-13.aspx?cmp=Insight-I1-2013-Art1

or just Google "parallel FFT cores"

You will find effective rates of up to 8 Gss available on a V7 easily.

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  • \$\begingroup\$ Thank you for your answer ! My work is already finished but I'm sure it will be useful for other people \$\endgroup\$
    – asonnino
    Commented Feb 22, 2016 at 18:20

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