I encounter a problem with the DAC on both STM32F4/STM32F429 Discovery boards and hope someone can give me a hint.
The DAC (using DMA with output buffer enabled) generates a FSK controlling signal sequence with only two steps, which looks like as follows
As can be seen on the screenshot, the settling time of the voltage step is about 6 ms! Since the signal sequence controls a very sensitive VCO, this long settling time results in a corresponding segment of output freeuency that is unusable for my application.
I am wondering, is this a problem of settling time? If yes, is there a way to alleviate it?
- The probe connects directly to the DAC pin, which is the only pin used in the measurement.
- I have calibrated my scope's probe.
- The STM32F4 discovery board is powered via the USB port.
With this setup, I tried to capture the rising edge of the step from 0 to 4000 using different time scales. The results are as follows: Compared to the above screenshot, the overshooting amplitude seems to be proportional to the step-voltage.
Due to my low reputation, I cannot post more than 2 links, but the zoom-in view shows a similar rising edge as @Arsenal's measurement. I think that is the real settling time.
I hope this update could lead to some new suggestions.