# Why 60% overshoot with 55° phase margin?

UPDATE: Based on the answers I received, I got this working beautifully. There's a full outcome report in one of the answers below.

I'm working through the design of an electronic load, basically a power MOSFET driven by an op amp.

I simulated the loop gain frequency response like this:

Producing a frequency response plot like this:

The 0dB frequency is 470kHz, with a phase margin of 55° and a gain margin of about 11dB.

All very satisfactory so far, but when I switch to step response like this:

I get an output waveform with 60% overshoot on both the rise and fall:

What's up with that? I thought phase margin and overshoot were directly related. and expected something with a very small amount of overshoot, or perhaps none at all.

Preliminary tests on the bench confirm the simulation. There is no oscillation, but step response shows a large overshoot. I have to do some mechanical and desoldering to get the signal generator input in there cleanly for a proper test.

I have a couple of hypotheses, but not enough experience yet to know which path is most profitable to pursue, or if the solution even lies in this list:

Hypothesis 1. The method I'm using to plot the loop gain frequency response is not applicable to this circuit for some reason or I've gotten it wrong somehow. I learned this approach from this Linear Technologies LTspice video: http://www.linear.com/solutions/4449

Hypothesis 2. Step response is not always directly tied to loop gain frequency response, and one of the capacitors or something is causing the step response to be strange even though the feedback loop is stable.

Can you help me understand where I've gone wrong?

I would go with Hypothesis 2.

I think, you have simulated the loop gain correctly. The input impedance at the inv. input seems to be much larger than the combined source impedance of the remaining network. I recommend to make another test and select another point for placing the test signal source: Between the opamp output and the common node of C2 and Riso. The result should be (nearly) the same as in your first simulation.

However, I tend to Hypothesis 2 because the known relation between overshoot and phase margin applies to second-order systems only. However, your system is of higher order (opamp 2nd order, FET 1st or 2nd order, two external capacitors). More than that, the simulation results clearly show an enhancement of the phase caused by C1 (improving stability). The mentioned relation between time and frequency domain does not allow such a zero.

UPDATE: I think, the form of the step response confirms my analysis: It does not show a typical "overshoot" (which should exhibit some ringing for such a large peaking). Instead, it shows the typical form for a step response of a highpass (caused by the capacitor C1)

• You were quite right @LvW; your observation about the overshoot sub-waveform was very insightful, I was wondering about the absence of ringing but didn't make the capacitive connection until you pointed it out. I ended up needing to remove both capacitors and abandon "in-the-loop" compensation altogether, and compensate by lowering the feedback percentage (raising closed-loop gain). I lost a little bandwidth but tuned it in at a very satisfactory 66.3° $ɸ_M$, 263kHz bandwidth, 2.8% overshoot, and 1µs rise time. I'll post details in a separate answer. Thanks again! :) – scanny Aug 7 '15 at 16:16

Outcome Report

Based on the accepted answer by LvW, I removed C1 to see if that would do the trick. Unfortunately no dice, as the waveform just changed to a different capacitive response:

However that was when I was sure LvW was right, and that using capacitors for compensation had to go. Who knew that using such a conventional compensation strategy could so negatively affect your step response? :)

I removed them both, along with $R_{iso}$, since there was no longer a need to isolate the gate capacitance, and adjusted the feedback resistors for a closed-loop gain of roughly 2.4.

and Voila!:

I was able to adjust the overshoot by manipulating the gain resistors, essentially moving the loop gain curve up and down to trade off bandwidth for phase margin. I settled on 66.3° $ɸ_M$, which yielded 263kHz bandwidth, 2.8% overshoot, and 1µs rise time. I want some extra stability in this particular circuit, and may even sacrifice a bit more bandwidth to achieve an extra margin of stability; a 1µs rise time is perfectly satisfactory for my purposes, and 2µs would be just fine too. I'll resolve all that on the bench.

So overall a very happy outcome this time. Thanks again LvW for your answer!

I also found Dave B's answer to be very helpful; I've been using the simple loop gain analysis method described in the Linear Technologies video referenced above for a few weeks now, but always with a bit of trepidation, very glad for the additional insight and resources Dave provided.

I would go with Hypothesis 1.

The LT technique works when your injection point has a high input impedance on one side, and a low source impedance on the other side. I tried to get that technique to work where my feedback network was pretty high impedance (yours is too), and ran into similar disagreement between measured circuit oscillation (I had negative margin!), simulated step response, and simulated phase-gain (using the LT technique).

When you run a phase-gain measurement with a network analyzer, say, with a power supply, you generally inject a signal into the feedback network by pushing against the low source impedance of the power supply output. A diagram showing this is on Page 8 of this application note on phase-gain measurements for DCDC converters.

In my case, when I moved the AC injection signal to push against a low impedance source (the output of my op-amp circuit) and into the high impedance feedback network, things started lining up.

In your case, there are two actually two feedback paths, one from the opamp output, and one from the sense voltage. Another power supply phase-gain reference may help here -- check out Venable Technical Paper 11 at Venable Industries for test configurations with multiple feedback loops. One of the techniques there may work for you.

Regarding Hypothesis 2, it is generally the other way around. You can have a nice looking step response (for a particular step with a favorable rise time) where the output phase goes all the way around. For other transients it might not be (ok, won't be) so favorable. Getting your hands on a network analyzer is the most definitive approach to confirming adequate phase margin, and also the most expensive option. And annoying to have to cut in to your proto.