Can you critique my design?

After finishing my 5v part, I've added the 35V part, too.

10-32V to 5V 1.2A SMPS Buck Regulator, the IC is IFX91041 from Infineon.

10-32V to 35V 4A SMPS Boost Regulator, the IC is LTC3786 from Linear Technology.

Here are the schematics and layouts in their original filetypes, in this case Proteus .DSN and .LYT files: MediaFire Server

Sorry for the big sized pictures, I wanted to be clear. For the partitioning of the layout, I have to say that when I use bitmap out-putter of Proteus ARES, it cannot output vias on the top layer, so I had to take a screenshot.

Also, sorry about the mess in schematics, just use it for designators, parts are not as they are, for example Q1 and Q2 are not IRFx.

SMPS PCB Design Critic 2

Schematics: Schematics

Top Layer Part 1: enter image description here

Top Layer Part 2: enter image description here

Bottom Layer: enter image description here

  • \$\begingroup\$ What is the question here? \$\endgroup\$
    – captncraig
    Aug 28, 2011 at 5:08
  • \$\begingroup\$ Oh sorry, I forgot to mention that due to other questions in mind. I want you to critique my design, give me advice. \$\endgroup\$ Aug 28, 2011 at 9:21
  • 2
    \$\begingroup\$ VIAs inside PADS is very bad for automatic smd mounting because solder go to via. \$\endgroup\$
    – user90403
    Oct 30, 2015 at 11:02

1 Answer 1


The fill areas seem overdone, especially where they fill way out into empty space that's far away from components rather than flowing between components, like at the corners of the board. I'd put more gap between small traces and large fills since there seems to be room for it - you don't want high-current fills right up against signal traces. I would not put fill around those standoff holes (TLP1 hole 1), at least not so close, since a wobbly or over-large standoff could scrape away the mask and short to the fill. Also for EMI you probably don't want a hole in a high-current fill, as those standoffs make. You've got some thin trace on TLP1 Q1, I'd push the fill below down towards C7/C18 and widen that trace a bit. You don't want ground running under L3 since you can pick up ground bounce that way.

The component pads need the fill to enter from only one side or otherwise have some thermal separation from the fill, otherwise the component may be hard to solder, as heat will flow away from the pad too quickly compared to small pads and the solder paste won't melt evenly. Similarly you may want the vias just a little farther from the pad on C14, C20, C21 as they will conduct some heat away to the other plane.

Don't know if you've considered height and how things are spaced for hand-done rework as you're debugging. I'd put L3 on TLP2 a little farther out from D3 or L3 will be pretty hard to hand solder without removing D3 first. If you can't fit a soldering iron tip between two large components they're too close together (if you have room to move them a bit, or can rotate one). I'd bring the connections to U2 pins 1/2/7/8 out a little like traces and then connect them together, instead of filling them side to side, because if you have to hand cut a trace or something it will be easier. Just some ideas from a brief look - I haven't considered component placement.


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