# PCB Layout and Trace Widths for Buck Converter

I am doing a PCB layout for a simple 12V DC to 5VDC buck converter. The rated output is 3A continuous 5A peak. Here are links to the schematic and first go at the pcb layout. I realize the traces are way to thin.

I am designing this based on the assumption I would use OSHPark to manufacture the board which uses 1oz thick copper layers. This means for the max 5A output I need the output current carrying traces to be 109mill. Currently they are 9.84mills. This leads me to a few questions mostly about current capacity.

1) If the load is drawing 5A will the output of the buck converter on the switching outputs be 5A? I'm assuming that it would be a fraction of that 5A based on the duty cycle but I'm not sure if thats an over simplification. Since the chip I used in my design has 3 switching output pins to share the current load but all together they are still less than half of the 109mill width.

2) The resistor branch is easy to calculate the current for ( 5V / 4.16K = 1.2mA ) so no concerns there at all. I'm assuming the diode should be rated at the 5A. What about the capacitor branches though? I'm not sure what current capacity those will need. I realize there is no electric current going through them but they are charging and discharging to smooth the ripple so there has to be some displacement current? Do I need to be thinking about this?

3) What size should my via's be? I have found plenty of calculators and tools for trace width but nothing about vias.

4) The 109mil trace for 5A is actually wider than the pad for my screw terminal. Should I just make those pads larger? Is there a general rule of thumb in terms of pad size verse the trace going into it? What about connections from the other parallel branches such as the feedback resistors. Is it ok to just drop a thinner trace onto a thicker one?

5) Any other feedback about what I have done with this PCB layout? Like I said its my first go at designing a PCB.

Note that I do not actually have an application in mind. The point of this exercise was to get experience with PCB layout and KiCAD. This is my first PCB layout. I will probably load it up with a dummy load to confirm it works and move onto the next project without it ever making it into a case or a finished product.

UPDATE: Revision 2

UPDATE: Revision 3

I realize there are probably still significant problems with this and that I already accepted an answer. Just including a "final" revision for completeness sake. At-least final kicad version. I may try redoing it in Eagle or something else.

• I should add that the footprints for C1/C4, H1/H2, U1 and L1 where created by myself. So if something looks off there that could by why. Aug 9, 2015 at 4:25
• Switchers are layout-sensitive (even when it's just a buck). Figuring out the layout for the switcher is not easy. Best thing is to reuse - as much as practical - the layout provided by the IC manufacturer. Sometimes, the recommended layout is drawn in the datasheet (example, p.12). Sometimes, the chip has an eval board and the layout is detailed in the eval board's manual. The recommended layout for your particular IC is nowhere to be found. It may be better to look for another IC with a published recommended layout. Aug 9, 2015 at 5:32
• I usually cut a void in the ground plane between the switching node and Vin to prevent reverse coupling the switching noise to the input. I also void everything under the inductor. As noted, switchers are complex to lay out and it is always prudent to follow the manufacturers guidance if it available. Aug 11, 2015 at 10:41
• Update 3 is approximately 1000x better. Still need some vias under the ground pad though! Aug 14, 2015 at 5:11
• While you're at it, connect the ground pour at C2 pad 2 to the U1 thermal pad, and remove some of the copper pour around C3. As already discussed, the mode that the switching node radiates is voltage/electric field, and that gets worse with surface area. As C3 is just a bootstrap cap, there shouldn't be a ton of current going through it. Aug 14, 2015 at 5:15

You should turn these traces into large copper pours.

You need to co-locate the capacitor with the output of the inductor. That will reduce noise in your circuit, since there is a large AC current flowing out of the inductor into the capacitor at all times.

Consider that the AC path into the capacitor needs to make its circuit back to the ground of the IC, and move it around accordingly.

Make your switching node as small as possible to eliminate noise.C3 looks pretty good, but after that it gets pretty tangled.

You need to add vias under the ground pad of the IC for heat conduction into the ground plane.

• FWIW, I have a triple buck converter where I've tried to optimize for small area (specifically, small loop area). This can be further improved by moving the voltage divider out of the way, and making the connections larger. Aug 10, 2015 at 5:18
• I rearranged the capacitors and tried to shrink the switching node as much as possible. I have attached the new layout. I was about to start adding pours but I am uncertain about the size switching node as you mentioned. Is physical proximity all that maters or does a larger copper pour mean more material for noise to radiate off of. Aug 11, 2015 at 6:15
• If this works well I would be shocked. Go read some Linear Technology switcher datasheets and see how they do the layouts. You have highly inductive paths to ground with narrow wires and single vias. You also have no way to get the heat out of U1. || Sorry man, this stuff isn't easy! Aug 11, 2015 at 15:16
• you don't need to bridge the massive pour to the IC pad with teeeny tiny wires, dont be afraid of fat traces! Aug 13, 2015 at 4:56
• 1. Connect nets with proper trace width (much fatter than signal trace) 2. Add pours as you can to supplement and as required (cleaner than a pure pour trace IMO) 3. RESPECT THE CREEPAGE ON HV TRACES 4. Study existing designs extensively (these are made en-masse, reliably, for a few dollars, don't reinvent the wheel) Aug 13, 2015 at 4:59