3
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This is the code I have implemented :

entity tinyMultiplier2X is
Port ( x : in  STD_LOGIC_VECTOR (3 downto 0);
       y : in  STD_LOGIC_VECTOR (3 downto 0);
       ml : out  STD_LOGIC_VECTOR (3 downto 0);
       mh : out  STD_LOGIC_VECTOR (3 downto 0);
       mc : out  STD_LOGIC);
end tinyMultiplier2X;

architecture Behavioral of tinyMultiplier2X is

component ThreeXthreeMultiply
    Port ( x : in  STD_LOGIC_VECTOR (2 downto 0);
             y : in  STD_LOGIC_VECTOR (2 downto 0);
             mul : out  STD_LOGIC_VECTOR (5 downto 0));
end component;

component Multi4x3
    Port ( x : in  STD_LOGIC_VECTOR (2 downto 0);
             y : in  STD_LOGIC;
             mul : out  STD_LOGIC_VECTOR (5 downto 0));
end component;

component FastBin2XDecConvert
    Port ( bin : in  STD_LOGIC_VECTOR (5 downto 0);
         dec : out  STD_LOGIC_VECTOR (8 downto 0));
end component;

signal b,s1,s2,s3,s4 : STD_LOGIC; --THIS IS LINE 59
signal p0 : STD_LOGIC_VECTOR(2 downto 0);
signal p1,p2,p3 : STD_LOGIC_VECTOR(5 downto 0);
signal p4,p5,p6 : STD_LOGIC_VECTOR (8 downto 0);

begin

s1 <= x(3) or y(3);
s2 <= x(0) or y(0);
s3 <= x(0) and y(0);
s4 <= x(3) and y(3);

m3x3 : ThreeXthreeMultiply port map(x(2 downto 0), y(2 downto 0), p1);

p0 <= y(2 downto 0) when x(3)='1' else x(2 downto 0);
b <= x(0) when x(3)='1' else y(0);

m4x3 : Multi4x3 port map(p0, b, p2);

p3 <= p2 when s1='1' else p1;

bndc : FastBin2XDecConvert port map(p3, p4);

p5 <= "101000100" when s2='1' else "100101000";
p6 <= "101100010" when s3='1' else p5;

ml <= p6(3 downto 0) when s4='1' else p4(3 downto 0);
mh <= p6(7 downto 4) when s4='1' else p4(7 downto 4);
mc <= p6(8) when s4='1' else p4(8);

end Behavioral;

ISE creates schematic but a warning exist and I think because of that syntheses report is not created. the warning is :

WARNING:HDLCompiler:946 - "C:\VHDL\SignificantSquarer\compactMultiplier.vhd" Line 59: Actual for formal port a is neither a static name nor a globally static expression

and is pointing to the place I have implemented my signals.

any help?

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  • \$\begingroup\$ There doesn't appear to be a line 59 in the code that you have posted... \$\endgroup\$ – Tom Carpenter Aug 9 '15 at 14:07
  • \$\begingroup\$ Sorry Editted , line 59 is were first signal is implemented \$\endgroup\$ – Alireza Tabatabaeian Aug 9 '15 at 14:31
  • 1
    \$\begingroup\$ You're looking at the wrong file, I think. \$\endgroup\$ – FRob Aug 9 '15 at 15:41
  • \$\begingroup\$ You are right , the error were found in one of the component's file. \$\endgroup\$ – Alireza Tabatabaeian Aug 9 '15 at 15:48
  • \$\begingroup\$ Your code needs your C type comment delimiter (//) changed to a VHDL comment delimiter (--) before it can be analyzed. Please add the correct file. \$\endgroup\$ – user8352 Aug 9 '15 at 17:46
7
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Finally after some seeking an answer showed up.

The full adder inside one of the components (ThreeXthreeMultiply) was not instantiated properly.

It was ported like this:

port map(A and B, f, cin, s, cout);

The problem is, in a port map no functions should be used. Changing to this code solved the problem:

s <= A and B; --s is a signal
port map(s, f, cin, s, cout);
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  • \$\begingroup\$ A question and an answer without the code in question doesn't seem useful to StackExchange readers. Also note // is not used as a comment delimiter in VHDL. \$\endgroup\$ – user8352 Aug 9 '15 at 17:46
  • \$\begingroup\$ Thanks! It is interesting why not it can't be used without another signal \$\endgroup\$ – Ivan Borshchov Apr 21 '16 at 20:40

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