The datasheet of the 24LC256 EEPROM states that:

The SDA bus requires a pull-up resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz and 1 MHz).

I thought that any resistor with a kΩ value would do the job (and it seems that my EEPROM works fine at different frequencies with a 10 kΩ resistor).

My questions are:

  • is there a correct value for pull-up resistors ?
  • is there a law/rule to determine this value ?
  • how do different resistance values affect the I²C data bus ?

The correct pullup resistance for the I2C bus depends on the total capacitance on the bus and the frequency you want to operate the bus at.

The formula from the ATmega168 datasheet (which I believe comes from the official I2C spec) is --

$$\text{Freq}<100\text{kHz} \implies R_{\text{min}}=\frac{V_{cc}-0.4\text{V}}{3\text{mA}}, R_{\text{max}}=\frac{1000\text{ns}}{C_{\text{bus}}}$$

$$\text{Freq}>100\text{kHz} \implies R_{\text{min}}=\frac{V_{cc}-0.4\text{V}}{3\text{mA}}, R_{\text{max}}=\frac{300\text{ns}}{C_{\text{bus}}}$$

The Microchip 24LC256 specifies a maximum pin capacitance of 10pF (which is fairly typical). Count up the number of devices you have in parallel on the bus and use the formula above to calculate a range of values that will work.

If you are powering off of batteries I would use values that are at the high end of the range. If there are no power limits on the power source or power dissipation issues in the ICs I would use values on the lower end of the range.

I sell some kits with an I2C RTC (DS1337). I include 4K7 resistors in the kit which seems like a reasonable compromise for most users.

  • \$\begingroup\$ Typically I would imagine the bus to be idle (de-asserted) the vast majority of the time, so for a battery application there are more important issues to deal with than trying to optimize I2C pullups just so :P \$\endgroup\$ – Nick T Oct 2 '10 at 3:02
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    \$\begingroup\$ only thing i would add is a buffer above the summed capacitance of the devices on the bus. The trace itself as well as the solder joints from pads to pins will also have some impedance. On longer buses the capacitance of the trace/wire can be larger than the pin capacitance of the devices. When designing production boards i don't usually determine the final pull up value till i have a prototype in hand and can scope the bus with various values. \$\endgroup\$ – Mark Oct 4 '10 at 2:01

It makes sense that higher frequencies require lower resistance pull-ups: a lower resistance will charge/discharge the cable's capacitance faster, which results in steeper edges. With the wider pulses of lower frequencies a less steep edge won't influence the pulse's shape as much.

Therefore the I2C specification gives maximum values for the pull-up resistors as a function of bus capacitance for three speed classes:

enter image description here

The minimum values are defined in function of the bus voltage, and should limit the current through the drivers.


There is a correct range of values, however it is difficult to describe exactly what that range is. Generally, 10k works.

Digital outputs have a specified ability to source or sink current. If your output could sink 5 mA and the output was connected through a pull-up to 5 V and then set to 0, you would need a minimum of 1k resistance. If you use less than 1k, the output will not be able to sink enough current to pull the pin all the way down to 0V. If you use a bigger value, like 10k, then the pin only has to sink 0.5 mA, which is much less than it's rating.

Digital inputs have a specified leakage current. This is kinda like the amount of current it takes to "maintain" a 0 or 1 at an input. If your pull-up resistor is too large, then it won't be able to overcome the leakage current. If it just barely overcomes the leakage current, then any noise in the circuit could be enough to change the input.

When using digital outputs that can sink and source current ("totem pole driver", "push-pull driver"), you might be tempted to not use pull-up or pull-down resistors. However, it is very important that CMOS inputs not be allowed to float or they can pull excessive current...and it's very easy to forget that bidirectional MCU pins usually come up as inputs!

I2C and other protocols like it use "open drain" (or "open collector") outputs. Instead of having outputs that can pull up and down, and open drain outputs can only pull down. That is why the external pull-up resistor is required. There are now additional restrictions on the range of pull-up resistors; the pull-up value will form an RC circuit with the bus capacitance. Too small of a value will once again prevent the output drivers from sinking enough current to pull the pin all the way down to 0. However, too large a value will take too long to charge the bus capacitance up.

If there are setup/hold times that you are not allowed to violate, those will help you determine an RC time constant. The bus capacitance is largely determined by PCB layout, so you can then pick an R value that combines with the C to provide a value that is comfortably within the setup/hold time for your digital input.


Low pull-up values (lower resistance) can improve the edges of the signal transitions but can sometimes be too stiff - if the devices on the bus cannot sink the pull-up current you get logic 'low' which isn't really that low, which can cause communication errors (and much pain.)

I would go with the highest pull-up resistance that gives you reliable communications.


For low frequencies the value doesn't really matter, but for high frequencies it can have a filtering effect on the signal, in combination with other capacitances in the circuit, which is why they recommend different values for different speeds.


An issue I haven't seen mentioned yet is power consumption. If one is using a 3.3 volt supply, a 3.3K resistor to ground will waste 1mA of current (3.3mW of power) whenever an output is low. Using a 10K resistor would reduce both current and power by a factor of three. If there will be a lot of communication on the I2C bus, that power consumption may end up being a significant portion of overall power drain especially if the bus may sit low for extended periods of time. For example, if one is reading 100 bytes/second but after reading each byte the bus is left with the device outputting the first bit of the next byte, and most of those bytes are have the MSB clear, the bus may spend 90% of the time with SCL and SDA low. Depending upon what else the system is doing, that could massively increase power draw.

To save power, it may be helpful to have a "pull-up" resistor connected to an I/O pin rather than to VDD. While I haven't seen hardware I2C implementations offer support for this, having the master output data on a separate I/O pin that's connected to the bus via resistor rather than using an open-collector driver and a fixed pull-up resistor will avoid wasting current when the master wants to output a "0". In addition, if the master is going to leave SCK low for awhile without caring about what's on SDA, the master may disable the pull-up until it's ready for some more communication. If none of the devices need to use clock stretching, the master can simply use a direct output for SCK and not bother with any pull-up on that wire.

If one is using software bit-banging with a fast processor, and one wants to get good performance despite high bus capacitance, the above approach can be combined with the use of a processor's built-in weak pull-ups. When reading data, turn on a very strong pull-up, briefly, immediately after each falling edge of SCK, and then switch to a weak pull-up. The strong pull-up will pull the line high despite the capacitance, and once the line is pulled high the weak pull-up will be able to keep it high. Even if a device would have trouble pulling the line low against the strong pull-up, it would be able to do so once the strong pull-up is switched off.


Minimal resistor value depends on driving capabilities of two sides of the bus. For example they drive 10 mA, so your resistor value should be greater than \$\frac{V_{bus}}{10~mA}\$. It is not exact resistor value, it depends on your bus capacitance. You can check your resistor value whether it is correct or not, by measuring rising time and falling time of bus pulses. You can find these time values in below link:



Here are waveforms, for 400kiloBits/second (200KHz 101010 waveform). The RC is 4.7K ohm and 212pF. The RC value allows 2 TAU settling.

enter image description here

  • \$\begingroup\$ This answer is just wrong. 200 kHz clock gives 200 kb/s, not 400. Only the rising edges are affected by the pull-up resistance. The plots look confusing, almost like there is some kind of modulation taking place. Physical quantities and their units are written with space (or thin space) in between. Tau is a symbol, not an abbreviation. \$\endgroup\$ – venny Apr 18 at 15:42
  • \$\begingroup\$ @venny This is typical waveforms for a bus running too fast for the settling time. With only 2 TAU settling, there is no flat-top to the waveforms, hence the "some kind of modulation"; were this a pseudo-random pattern, the variability of settling would be very obvious; read up on "data eye". Finally, the 200KHz clock has high for 2.5uS then low for 2.5uS; the period of 2.5uS is exactly the 400KHz data I mentioned. \$\endgroup\$ – analogsystemsrf Apr 18 at 15:48
  • \$\begingroup\$ This answer does not reflect I2C waveforms. The falling edge is always fast on I2C. \$\endgroup\$ – Timmy Brolin Nov 26 at 18:14

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