Suppose I have 3 signals generated by NMOS logic. Each of those signals has an associated enable pin that when driven high will result in the value of the signal appearing on the output (I should note that signals A,B,C originate in different areas of the circuit so using an OR gate to combine the enable signals would be inconvenient). I came up with a way I think should work, its circuit diagram shown below.
EDIT: An elaboration on the application I would want to use this in: I have a series of registers, and each one has an enable pin. When a registers enable pin is high I want the value stored in the corresponding register to appear on a bus
In CMOS logic something similar could be accomplished by setting the pins disabled to high impedance and having only the enabled pin driving the output line (this would require only one enable line is high at a time- which is something that is true anyways).
My questions is are there any drawbacks to the method I have on the circuit diagram? I am aware that the speed the coquet can run on is limited by the time the output line can rise, and that the circuit will consume more power than the CMOS version.
Im particularly interested in the amount of signals this could work with and anything else I should know about before implementing this on a PCB.