I wanted to ask, what general layout guidelines and/or routing concerns exist for I2C in a PCB design?

Edit - Consider a 31mil thick, 4Layer PCB with stack up:

  • L1 = signal - 0.5oz + 1oz plating
  • L2 = ground - 1oz
  • L3 = Pwr/ground - 1oz
  • L4 = pwr/ground - 0.5oz + 1oz plating
  • FR4 dielectric

Let's say you need to route across a 10 inch PCB (just for example sake) covering 2 inches on Layer1, 6 inches on Layer3, and 2 inches on layer1. What would be the design guidelines for this?

At high frequency, your SCK (clock) can couple easier to adjacent nets than at lower frequency. The same could apply to SDA (data), however this would be in regards to driver strength of the chip and the rise time associated with the signal. Are there any other oddities that exist with I2C in regards to behavior?

With this in mind, is it best to route SDA and SCK on different layers (assuming high freq) to avoid coupling between them? What is considered high frequency for these signals? Is there a standard routing methodology anyone uses? Typical to put a guard trace in betweeen them to minimize the coupling? What about vias in the middle of the traces to test pads?

  • 3
    \$\begingroup\$ High frequency I2C is standard 400kHz. Where are these 100MHz are coming from? \$\endgroup\$
    – Eugene Sh.
    Commented Aug 11, 2015 at 19:03
  • 1
    \$\begingroup\$ It's only 100kbps and the edges are slow too as that's an open-drain bus. (Well, the falling edge is a little faster) What can possibly go wrong at such low frequencies? \$\endgroup\$
    – Alexxx
    Commented Aug 11, 2015 at 19:07
  • 1
    \$\begingroup\$ @EugeneSh. Sorry I was thinking of a differential speed @ 100MHz in my head when writing this out. Good to know about the 400KHz, I didn't know that was a standard speed. \$\endgroup\$
    – Jacob C
    Commented Aug 11, 2015 at 19:25
  • \$\begingroup\$ Hate to see the down vote on the post, but that's OK, helps me learn. So based on the two comments above, it sounds like there is no real critical routing concern for both SDA and SCK. Is the topology for I2C more important than the routing concerns? \$\endgroup\$
    – Jacob C
    Commented Aug 11, 2015 at 19:28
  • \$\begingroup\$ There are also more recent 1 and 5 MHz standards. \$\endgroup\$
    – Matt Young
    Commented Aug 11, 2015 at 19:31

1 Answer 1


Wihtout knowing the constraints of your board real-estate and existing layout (i.e. is this a new design where you have free-reign, or must you shoehorn in I2C).

One technique I've had success with is separating on either side of SDA/SCL with a guard trace (ground). This way any emissions from the edges of those signals would be greatly attenuated and would be much less likely to couple into each other or into other signals. (Think the boyscout rule).

The other thing you'll have to evaulate is how much parasitic capacitance there would be in total from end to end. The I2C spec has an upper limit on capacitance to ensure the proper rise/fall/setup times, depending on the data rate. To calculate this you'll need to at least have an estimate of the trace length and a lookup table depending on your board layer stackup, the PCB material (FR4?), and the dimensions of the traces.

If there are any ESD susceptibility parts near the I2C now, move them!, or be prepared to either re-spin/engineer or add I2C retries in your code.

  • \$\begingroup\$ Thanks for your post. I wanted to ask, when you say parasitic capacitance, is this the same as load capacitance? For this link I found (cds.linear.com/docs/en/product-selector-card/2PB_i2Ca.pdf), they are stating that the capacitance load is 400pF. Is this what will affect my rise/fall/setup times and valid data? \$\endgroup\$
    – Jacob C
    Commented Aug 11, 2015 at 20:04
  • \$\begingroup\$ Exactly. The "load" implies the upper limit due to parasitics between the signal trace, the PCB material and the ground plane (think parallel plate capacitor). So long as you are (I would say well) under that 400pF limit depending on the data rate, you should be well on your way to a successful layout. \$\endgroup\$
    – cowboydan
    Commented Aug 11, 2015 at 20:16
  • \$\begingroup\$ Your guard traces are going to add significantly to the parasitic capacitance, especially if there is a ground plane. \$\endgroup\$
    – Matt Young
    Commented Aug 11, 2015 at 20:18
  • \$\begingroup\$ @IHeartStarWars - yup. Good luck! \$\endgroup\$
    – cowboydan
    Commented Aug 12, 2015 at 2:16
  • \$\begingroup\$ @cowboydan You said "One technique I've had success with is separating on either side of SDA/SCL with a guard trace (ground)." How is a trace connected to the ground net not part of the circuit? \$\endgroup\$
    – Matt Young
    Commented Aug 12, 2015 at 2:58

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