I wanted to ask, what general layout guidelines and/or routing concerns exist for I2C in a PCB design?
Edit - Consider a 31mil thick, 4Layer PCB with stack up:
- L1 = signal - 0.5oz + 1oz plating
- L2 = ground - 1oz
- L3 = Pwr/ground - 1oz
- L4 = pwr/ground - 0.5oz + 1oz plating
- FR4 dielectric
Let's say you need to route across a 10 inch PCB (just for example sake) covering 2 inches on Layer1, 6 inches on Layer3, and 2 inches on layer1. What would be the design guidelines for this?
At high frequency, your SCK (clock) can couple easier to adjacent nets than at lower frequency. The same could apply to SDA (data), however this would be in regards to driver strength of the chip and the rise time associated with the signal. Are there any other oddities that exist with I2C in regards to behavior?
With this in mind, is it best to route SDA and SCK on different layers (assuming high freq) to avoid coupling between them? What is considered high frequency for these signals? Is there a standard routing methodology anyone uses? Typical to put a guard trace in betweeen them to minimize the coupling? What about vias in the middle of the traces to test pads?