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Good morning everyone,

I'm building a device that uses several bidirectional logic level translators to interface 3.3V microcontroller to 5V, 2.5V and 1.8V sensors (via I2C lines).

But I wonder if level shifters produce any significant noise; this is interesting for me due to extensive use of MOSFETs, internal current sources and one-shot pulse devices in level shifters (please see MAX14548E as an example).

I'm asking because I haven't seen any mention of noise characteristics in specs of any of LLT devices.

Is noise a problem with level shifting, or should I put my worries to rest?

Thank you.

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  • \$\begingroup\$ What kind of noise are you worried about? I would not rco \$\endgroup\$ Aug 12, 2015 at 18:06
  • \$\begingroup\$ @SpehroPefhany well, I mean just any kind of signal distortion for a bus that runs at 100 kHz. \$\endgroup\$ Aug 12, 2015 at 18:10
  • \$\begingroup\$ The one you mention has a lot of channels and can switch very fast so it might introduce power or other noise, but so would a 16channel 100MHz buffer. \$\endgroup\$ Aug 12, 2015 at 18:13
  • \$\begingroup\$ define significant \$\endgroup\$ Aug 12, 2015 at 18:28
  • \$\begingroup\$ @OlegMazurov "strong enough to disrupt the integrity of a signal" let it be. \$\endgroup\$ Aug 13, 2015 at 15:11

2 Answers 2

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The current sources simply represent the device's internal pullups on the data lines.

The pulse generators are not part of the device at all, but rather part of the test setup used to demonstrate the device's performance.

None of this will contribute any significant noise in your application.

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The datasheet of the MAX14548E says:

To reduce ripple and the chance of introducing data errors, bypass VL and VCC to ground with 0.1μF ceramic capacitors. Place all capacitors as close as possible to the power-supply inputs. For full ESD protection, bypass VCC with a 1μF ceramic capacitor located as close as possible to the VCC input.

The manufacturer also guarantees a 100Mbps data rate. With I2C the maximum you can achieve is 3.4Mbit per second, in High Speed Mode. So I do not think that you have to worry about signal distortion because you will be much slower than the maximum capability of this IC. If you put those bybass capacitors on the \$ V_L \$ and \$ V_{CC} \$ lines, probably there won't be any problem, at least not because of the level-shifter.

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