Let's say I have a 5V pulse train that varies between 0 and 75000 pulses per second. Pulse width, let's say, is 5 microseconds. How could I calculate or determine the best way to filter out all pulses less than 4 microseconds in width?
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2\$\begingroup\$ Do you have a clock available? You could use a counter that counts the number of fast clock cycles for each pulse. A 10 MHz clock could get around 200 ns resolution. Then you could use that signal to only allow long enough pulses through, gating a delayed version of the pulse train. Do you have an FPGA or microcontroller in your system already? \$\endgroup\$– JustinCommented Aug 12, 2015 at 18:15
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3 Answers
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This circuit should do what you want:
When a pulse comes in on the lead marked IN, it starts the first 74221 monostable (there are two in the same package) which is set for 4 µs. The output of the monostable \$\small \overline{\text{Q}}\$ pin will be 1 until it is started, then it goes to 0. So during the 4 µs period, the AND gate (74HCT11) is inhibited so there is no output. After 4 µs, the AND gate is enabled again, so the rest of the pulse (if longer than 4 µs) goes through to OUT. See the timing diagrams below.
Since 4 µs has been cut off the beginning of any valid pulse, the second monostable is started on the falling edge of the input pulse (but only if it is longer than 4 µs), and the output remains high to add an additional 4 µs to the end of the output using the OR gate (74HCT32). Thanks to stefandz for pointing out the need for this additional functionality.
The buffer marked DS1100Z at the bottom is actually a delay line with a delay of 100 ns; this is to compensate for the propagation delay in the 74123 from trigger to output.
Note because of the tolerance of the capacitor, this timing could be off by 10%, so the resistor should be tweaked as necessary.
By using monostables, it is trivially easy to modify the timing value from 4 µs to something else just by changing a the resistors and/or capacitors.
Power pins (Vdd and Vss) and decoupling caps are not shown.
I was originally going to use a 555 timer, but it turns out the 555 is not supposed to be used for pulse widths less than about 10 µs. So I turned to the 74221, which can generate pulses down to the ns range.
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1\$\begingroup\$ If I understand this correctly, this also trims 4us off all pulse lengths which may be of consequence. \$\endgroup\$– stefandzCommented Aug 12, 2015 at 19:54
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1\$\begingroup\$ @stefandz I realize that; I don't know any other way to handle that, because you need to look at the pulse for 4 µs before deciding whether to throw it away or not. If you started to pass all pulses through immediately, and one turned out to be less than 4 µs, you've defeated the purpose of the circuit. \$\endgroup\$– tcrosleyCommented Aug 12, 2015 at 21:29
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1\$\begingroup\$ it's not necessarily an issue - but I would put it in the answer to make it clear to the asker. There is a way around this - in a circuit with memory, such as that by supercat you simply inspect and delay, thus preserving pulse lengths, but introducing a delay to the pulse train. \$\endgroup\$– stefandzCommented Aug 12, 2015 at 21:32
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1\$\begingroup\$ @stefandz Since the 74123 is a dual timer, I should be able to add a 4 µs delay at the end of the pulse, to compensate for the 4 µs lost at the beginning. Back to work. \$\endgroup\$– tcrosleyCommented Aug 12, 2015 at 21:46
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1\$\begingroup\$ now that would be a very neat answer, as it is lower in component count and doesn't have any sampling artefacts :) \$\endgroup\$– stefandzCommented Aug 12, 2015 at 21:48
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In many cases, the simplest approach is to use a synchronous logic circuit which samples the incoming signal at some rate (e.g. 10MHz), ensures that it's synchronized to that clock (passing it through a couple flip flops is a typical way to do this), and then applies whatever logic is needed in purely-digital fashion.
simulate this circuit – Schematic created using CircuitLab
The middle box in the circuit above is a six-bit synchronous-reset counter; every clock pulse will either reset it to zero (if RS is low) or advance the count (if high).
As shown, the circuit will reset the counter on each cycle where the out matches the synchronized value of the input, or increment the counter if they don't match. If there are 48 consecutive cycles where they don't match, the Q4 and Q5 of the counter will both be high. On the next cycle, the counter will be reset (regardless of what the input does) and the output will change state.
If the clock is 10Mhz, This circuit will filter out both high and low pulses shorter than roughly 4.9us, and will round all pulse timings to the nearest 100ns. There are many ways to vary the circuit to implement various kinds of filtering, but the key point is that the input is synchronized to a 10MHz clock and everything else in the circuit runs off the same clock.
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\$\begingroup\$ I presume you didn't intend to connect Q and !Q together in your schematic ;) \$\endgroup\$ Commented Aug 13, 2015 at 20:21
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I'd prefer to put this in a comment but cannot.
Since no error spec was given, is it possible, to switch from a time domain problem to a voltage again, by integrating the pulses and using a comparator...?
The 0-75kHz range is inconsequential I think and we only need care about the pulse width, ~4us. If the OP can get a reasonably linear rising edge this might work...?
Cheers
