My book says that by varying Vgs the transconductance varies in a non linear fashion (this all happens in the "linear" or ohmic region of the FET) and it is constant in the saturation region.I just cannot get it!!
Take a look at this, the (fairly) standard characteristic of a FET: -
Transconductance or "current out to volts in" is quite different between the linear region and the saturation region. In the saturation region if you lift the gate voltage from 4 V to 5V you get a corresponding change in the drain current of about 17mA to about 24mA and both ratios are about the same - not perfectly the same but enough to say that "transconductance is fairly constant in the saturation region".
The saturating transconductance varies a little bit with drain-source voltage and so it's not a perfect thing to say BUT people do say it and design circuits assuming it is a reasonable axiom.
Go to the linear region and note that for a given gate voltage (say 4V) the drain current is near enough totally dependant on drain voltage. People use this area as variable resistors - the gate controls the resistance between drain and source. Increase the gate voltage and the resistance lowers. It's more appropriate to call this section the linear (ohmic) region because there is no singular dependancy of drain current on gate voltage.
As a footnote, if you see a FET characteristic drawn like below where all the lines from 0,0 seem to merge into one until the saturation region begins to break them out individually, I have one thing to say and that is "THIS IS DRAWN WRONG": -