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When I want to simulate the following code, I get these errors:

"Unresolved reference to 'countmode1'"
"Unresolved reference to 'countmode2'"
"Unresolved reference to 'countmode3'"
module a8bitCounter(inp[7:0], ocrn, counter[7:0]);

  input [7:0] inp;
  input ocrn;
  output [7:0] counter;
  reg [1:0] countmode;
  reg [1:0] clksource;
  reg done, clk, reset, oc;
  reg round = 0;
  `include "countmode_1.v" // task functions included here
  initial
  begin
  countmode = {inp[3], inp[6]};
  clksource = inp[2:0];
  end
  parameter S0=3'b001 , S1=3'b010 , S2=3'b011 , S3=3'b100 , S4=3'b101, S5=3'b110 ,         S6=3'b111 , S7=3'b000 ;
   always @ (posedge clk, reset) begin
   if (inp[2:0] == 0) begin
end else if(clk)
begin
case (clksource)

    S0:begin

      if (countmode == 2'b00) begin
        countmode1(reset, counter, clksource, ocrn, oc, round, S0, S7);
      end

      else if (countmode == 2'b01) begin
        countmode2(reset, counter, clksource, ocrn, oc, round, S0, S7);
      end 

      else if (countmode == 2'b10) begin
        countmode3(reset, counter, clksource, ocrn, oc, round, S0, S7);
      end
    end

    S1:begin

      if (countmode == 2'b00) begin
        countmode1(reset, counter, clksource, ocrn, oc, round, S1, S7);
      end 

      else if (countmode == 2'b01) begin
        countmode2(reset, counter, clksource, ocrn, oc, round, S1, S7);
      end

      else if (countmode == 2'b10) begin
        countmode3(reset, counter, clksource, ocrn, oc, round, S1, S7);
      end
    end

    S2:begin

      if(countmode == 2'b00) begin
        countmode1(reset, counter, clksource, ocrn, oc, round, S2, S7);
      end 

      else if(countmode == 2'b01) begin
        countmode2(reset, counter, clksource, ocrn, oc, round, S2, S7);
      end 

      else if(countmode == 2'b10) begin
        countmode3(reset, counter, clksource, ocrn, oc, round, S2, S7);
        end
      end
      endcase
    end
    end
endmodule

This is part of an eight bit counter . I used following task functions to write it :

module countmode();
  reg reset , oc , round=0; 
  reg ocrn;
  reg [2:0] S0,S1,S2,S3,S4,S5,S6,S7;
  reg [7:0] counter;
  reg [1:0] clksource;



  task countmode1;
            if(reset) begin
              counter = 8'b0;
              clksource = S0;
            end 
            else if(counter == ocrn) begin
              oc = 1;
              clksource = S7;
            end else if(round == 5) begin
              round = 0;
              clksource = S7;
            end else if(counter == 8'b1) begin
              counter = 8'b0;
              round = round + 1;
              clksource = S0;
            end else begin
              counter = counter + 1;
              clksource = S0;
            end
 endtask

   task countmode2;
            if(reset) begin
              counter = 8'b0;
              clksource = S0;
            end else if(counter == ocrn) begin
              oc = 1;
              clksource = S7;
            end else if(round == 5) begin
              round = 0;
              clksource = S7;
            end else if(counter == 8'b1) begin
              counter = counter - 1;
              round = round + 1;
              clksource = S0;
            end else begin
              counter = counter + 1;
              clksource = S0;
            end
 endtask

   task countmode3;
            if(reset) begin
              counter = 8'b0;
              clksource = S0;
            end else if(counter == ocrn) begin
              counter = 8'b0;
              oc = 1;
              clksource = S7;
            end else if(round == 5) begin
              round = 0;
              clksource = S7;
            end else begin
              counter = counter + 1;
              round = round + 1;
              clksource = S0;
            end
 endtask
 endmodule

Please tell me how to fix this simulation error. I can't remove "always" because of the "if-else" functions.

EDIT : edited and add first part of source code.

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  • \$\begingroup\$ Please format your code. Which simulator do you use? \$\endgroup\$ – Paebbels Aug 16 '15 at 18:27
  • \$\begingroup\$ I use Modelsim . What do you mean by formating the code ? \$\endgroup\$ – Saeeds255 Aug 17 '15 at 2:02
  • \$\begingroup\$ Your passing arguments to tasks that don't have input/output; that's not allowed. Is this in the same module? A task should only be called within its module. Do you want something synthesizable? \$\endgroup\$ – Greg Aug 17 '15 at 2:50
  • \$\begingroup\$ @W5VO formatted and indented your code lines. So now we can read them all. Normally, it's your task to present a good structured and readable question. \$\endgroup\$ – Paebbels Aug 17 '15 at 6:23
  • \$\begingroup\$ @Greg The task codes is in another module but I included the file name in the main module . Why they should be in the same module when I used "include" ? Actually the file compiled successfuly but I get this error when I want to simulate it using Modelsim ! \$\endgroup\$ – Saeeds255 Aug 17 '15 at 10:56
1
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As @Greg pointed out, you are passing more number of arguments to tasks than required.

Also, including a file doesn't mean having access to all the tasks and functions inside the module. You have to instantiate the module inside your main a8bitCounter module as follows:

// `include "countmode_1.v" // include this file outside module will be good.
module a8bitCounter(inp[7:0], ocrn, counter[7:0]);
// ...
// ...
`include "countmode_1.v" // including here is not a common practice
countmode c1(); // instantiate the module
// ...
// ...
c1.countmode1(); // note the hierarchy path to the task
c1.countmode2(); // note the hierarchy path to the task
c1.countmode2(); // note the hierarchy path to the task
// ...
// ...
endmodule

If your countmode module is not required, then remove it and after that, the tasks shall be declared in global compilation unit scope. By, this you can directly use task names while invoking them (no need of hierarchy then,since they'll be in global scope). However, you must provide some input/output arguments to these tasks.

For more information on instantiating module in verilog, refer to this link. Tasks/functions in verilog can be found in this PDF.

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