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I am learning VHDL and I am using the Lattice boards. I want to know how to declare a GPIO. I found the following block of code in the diamond software folder example. It is ".lpf" file and I guess it is the place where the pin are declare. Can anyone explain simply what the lines mean:

BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
BLOCK JTAGPATHS ;
IOBUF ALLPORTS IO_TYPE=LVCMOS33 ;
LOCATE COMP "seg_1" SITE "V6" ;
LOCATE COMP "seg_2" SITE "U7" ;
LOCATE COMP "seg_3" SITE "Y6" ;
LOCATE COMP "seg_4" SITE "AA6" ;
LOCATE COMP "seg_5" SITE "U8" ;
LOCATE COMP "seg_6" SITE "T8" ;
LOCATE COMP "seg_7" SITE "AA5" ;
LOCATE COMP "seg_8" SITE "AB4" ;
LOCATE COMP "clk" SITE "L5" ;
IOBUF PORT "seg_1" IO_TYPE=LVCMOS33 TERMINATEVTT=OFF ;
LOCATE COMP "reset" SITE "J7" ;
IOBUF PORT "reset" IO_TYPE=LVCMOS33 ;
LOCATE COMP "direction" SITE "J6" ;
LOCATE COMP "LOCK" SITE "W5" ;
LOCATE COMP "seg_9" SITE "Y20" ;
LOCATE COMP "seg_10" SITE "AA21" ;
LOCATE COMP "seg_11" SITE "U18" ;
LOCATE COMP "seg_12" SITE "U19" ;
LOCATE COMP "seg_13" SITE "W19" ;
LOCATE COMP "seg_14" SITE "V19" ;
LOCATE COMP "seg_15" SITE "AB20" ;
LOCATE COMP "seg_16" SITE "AA20" ;

Correct me if I am wrong, so The first 3 lines block the user to use Pins that are used in JTAG & Reset?

A line like this:

LOCATE COMP "seg_16" SITE "AA20" ;

mean to the synthetizer that the variable seg_16 from the VHDL files is linked to the "real" pin of the board.

Finaly, I got no idea what the IOBUF keyword mean. So Did I get something right or I am plain wrong?

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    \$\begingroup\$ This isn't VHDL at all. This is one specific FPGA's pin constraint file. Your understanding is OK. The IOBUF constraint specifies the type of circuit connected to the pin - does it accept 2.5V, 3.3V or possibly 5V, does it have termination or pullup resistors, etc. (There should probably be one for each pin, so than seg_2 to seg_16 match seg_1) \$\endgroup\$
    – user16324
    Commented Aug 19, 2015 at 8:41
  • \$\begingroup\$ @BrianDrummond I know that it isn't VHDL, but I got this question after writting an OR gate Architecture and I wonder how to link your VHDL code to the pins. From what I have searched, It really depend of what synthetizer you are using. Each environnement got their syntax for connecting VHDL variable to actual NETs. (correct me if I am wrong) \$\endgroup\$
    – MathieuL
    Commented Aug 19, 2015 at 14:45

1 Answer 1

Reset to default
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The *.lpf file does indeed describe the pinout of the FPGA, however before explaining the lines, you should know that there is an easier way to assign them using the Lattice Diamond design software and there are some great tutorials out there showing how to do this, I've just found this one: https://youtu.be/SmdEP_ZsBgM

He starts assigning pins at about 17:15 but it's worth watching the whole thing so you can see the process from start to finish.

To give you an idea of what the lines in the lpf file mean here are a few examples:

IOBUF ALLPORTS IO_TYPE=LVCMOS33 ; = Set all ports to use the 3V3 Low Voltage CMOS logic standard.

LOCATE COMP "seg_1" SITE "V6" ; = Assign the port named "seg_1" to pin V6.

Hope this helps,

Gipsy

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