# WFI instruction slowing down SYStick interrupt

I've configured my Infineon relax kit for max frequency(120 MHz). I've set my SYSTick for a periodic interrupt of 10 ms. For power saving, I use a WFI assembler instruction whenever my processor is idle. WFI (wait for interrupt) should put the processor in low power mode until an interrupt occurs. So my processor should wake up after every 10 ms. But somehow, this WFI instruction slowed down my interrupt frequency to almost 3 times and it wakes up on every third interrupt. What can be possible reason for WFI not waking up on every interrupt?

• Does the datasheet say anything about how long it takes to wake up from low power mode? Does it also mention the interrupt latency and any delay in getting to max frequency? Can you provide a link to the datasheet? Which clock runs during low power mode? – Roger Rowland Aug 19 '15 at 12:04
• How do you know that it only wakes up every third interrupt? Is it possible that your MCU goes into some deeper sleep mode, which reduces the core frequency? – corecode Aug 19 '15 at 12:06
• Link to the datasheet: keil.com/dd/docs/datashts/infineon/xmc4500/xmc4500_um.pdf Datasheet does not say anything about interrupt latency. I've enabled system clock(CCU) in SleepCR register to counter any effects of clock gating but to no avail. @Roger Rowland – Saqib Ahmed Aug 19 '15 at 12:38
• @corecode I have a variable that increments on every systick interrupt. Without WFI, it increments to a 1000 in 10 seconds, but with WFI, it increments to only 330. So this means that my interrupt's been handled on every third call. Or alternatively, my effective frequency has reduced to 3 times. My MCU goes in sleep mode(not deep sleep) by default. – Saqib Ahmed Aug 19 '15 at 12:43
• Cortex M4F need 6 cycles to get back up from normal WFI, shouldn't be a problem if the clocks stay the same (which I try to find out but the user manual is horrible). Can you output the clock used for systick and probe what happens if you go to WFI? – Arsenal Aug 19 '15 at 14:36

I'm not familiar with these devices, but in the user manual it is mentioned that:

The Sleep state of the system corresponds to the Sleep state of the CPU. The state is entered via WFI or WFE instruction of the CPU. In this state the clock to the CPU is stopped. The source of the system clock may be altered. Peripherals clocks are gated according to the SLEEPCR register.

Taking a look at the SLEEPCR register description shows:

Field  Bits Type Description
SYSSEL 0    rwh  System Clock Selection Value
0 -> f OFI clock, 1 -> f PLL clock


as the reset value of said register is 0, it defaults to the $f_{OFI}$ clock. Which runs at 36.5 MHz uncalibrated or 24 MHz calibrated. It has a rather huge accuracy range if uncalibrated (see the datasheet) of at least +-15%, together with the fact that you will get some systicks with 120 MHz in again during your execution it might well turn out to be roughly 40MHz in average.

Solution (hopefully): Set the SYSSEL bit to 1.

• Thanks for the tip. It didn't occur to me. I was setting CCU bit in SLEEPCR register. – Saqib Ahmed Aug 19 '15 at 14:53